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Title
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Customer Rating
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Updated
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NoBL Burst and Standard NoBL differences
What are the differences between the standard NoBL and the NoBL Burst 72M SRAMs?
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Not yet rated
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06/18/11 |
NoBL Sram Definition
What is a NoBL SRAM?
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(5/5) by 1
user
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06/18/11 |
Package selection of Synch SRAMs
What are the selection criteria in selecting a package for Synchronous SRAMs?
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Not yet rated
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06/18/11 |
Sync Burst SRAM Deselect Sequence
How do we deselect a Sync Burst SRAM?
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Not yet rated
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06/18/11 |
Use of ADV/LD pin
What is the use and the function of the ADV/LD pin?
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Not yet rated
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06/18/11 |
CY2308 configuration of S1 and S2
If S2=1 and S1=0, then as per the datasheet, the output source is reference instead of PLL. What will the propagation delay be in this case?
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Not yet rated
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06/18/11 |
CY2302 Transistor Count, Technology and Gate Count
What is the technology, die size, transistor and gate count for CY2302?
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Not yet rated
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06/18/11 |
Maximum junction temperature and Theta JC thermal resistance of CY2302SXI-1 part
What are the values of Maximum junction temperature and Theta JC thermal resistance of CY2302SXI-1 part?
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Not yet rated
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06/18/11 |
CY23FS08 Input Switching Behavior with an External Mux
When an external mux is used with the need to have more that 2 inputs, do we have glitches passing from an input to another?
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Not yet rated
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06/18/11 |
UDMA Mode Support with ISD-300A1
Since ATA-34pin(CBLID#) can be used to limit UDMA mode support, should UDMA be limited to UDMA mode 2? How does the ISD-300A1 determine the device protocol?
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Not yet rated
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06/18/11 |
Maximum Input frequency for T0, T1, T2 inputs
What is the maximum frequency for the T0, T1, T2 inputs?
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Not yet rated
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06/18/11 |
eeprom.c and eeprom.h files missing in Vend_Ax example.
I recently downloaded and installed the CY3684 development kit software. When I try to build the Vend_Ax example I get an error message saying that the eeprom.c and eeprom.h files are missing. What should I do?
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Not yet rated
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06/18/11 |
Intermittent IMODE Operation Using the ISD-300.
Is Intermittent IMODE operation in ISD-300 a known bug?
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Not yet rated
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06/18/11 |
Programming the ISD-300
How to program the ISD-300?
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Not yet rated
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06/18/11 |
Bulk Command Failures with an ISD-300.
Bulk commands with a DTL of 0xFFFF will fail on UDMA devices with an ISD-300.
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Not yet rated
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06/18/11 |
Registering KEIL compiler of PSoC Creator in a PC without Internet connection
For registration of free Keil C licensing, we are required to connect to Internet through PSoC Creator tool. However, we do not have our computer connected to internet. Do we have any option to register the free Keil C license without PSoC Creator tool installed PC?
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(3/5) by 2
users
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06/18/11 |
Getting "Keil License expired" error message in PSoC Creator
When I compile project using PSoC Creator, I get following error:
"ERROR: Keil License expired. Obtain a valid Keil license and update the information through your installed version of Keil or in PSoC Creator"
How to remove this error?
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Not yet rated
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06/18/11 |
CY8CKIT-023 EBK Example Projects Build Failure with PSoC Creator 1.0 and PSoC 3 Production Silicon
How to successfully build the example projects found in "CY8CKIT-023 PSoC Expansion Board Kit For iPhone & iPod Accessories" with PSoC Creator 1.0 (and PSoC Creator 1.0 SP2 software) and the production version of PSoC 3 silicon?
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(1/5) by 4
users
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06/18/11 |
Requisite of capacitors for Vcca/Vdda to Vssa even if Analog components are not being used in PSoC 3/5
Are the capacitors from Vcca/Vdda to Vssa needed if the Analog components are not used in PSoC 3/5?
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Not yet rated
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06/18/11 |
"CYDEV_SFR_USER_CPUCLK_DIV undefined error" from PSoC Creator with PSoC 3
I'm getting "CYDEV_SFR_USER_CPUCLK_DIV undefined error" error message while updating a project to PSoC Creator 1.0 & ES3 Silicon. How to resolve it?
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Not yet rated
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06/18/11 |
Renumeration in firmware for FX1/FX2LP
How can I do renumeration in firmware?
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Not yet rated
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06/18/11 |
Ways of configuration of Endpoints 2,4,6 and 8 in FX1/FX2LP
What are the ways in which endpoints 2,4,6 and 8 be buffered?
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Not yet rated
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06/18/11 |
Read / Write control signals on unidirectional FIFOs
Why is there a read/write control signal (R/W#) on each port for a unidirectional FIFO?
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Not yet rated
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06/18/11 |
Writing at the Full Boundary
- What happens if FIFO is continuously write into when Full Flag is asserted?
- My system is set up to continuously write until the FIFO is full. Once it is full, I begin to read out the data. However, it seems like I lose some of the data being written into the FIFO when I do so. RCLK and WCLK are the same. What is wrong?
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Not yet rated
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06/17/11 |
PIO and UDMA Settings of the ISD-300A1
How to distinguish between the PIO and the UDMA settings?
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Not yet rated
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06/17/11 |
Usage of the Output Enable (OE) Signal in Synchronous FIFOs
1. If OE is high, what happens to the data bus?
2. If there is a valid read operation, but OE is high, will the next read operation be the same word or the following word in the FIFO?
3. If OE is high during reset, will the data bus remain in a high-Z state?
4. Is it okay to connect the OE pin to ground?
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Not yet rated
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06/17/11 |
High speed monitor
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Not yet rated
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06/17/11 |
Synchronous FIFO architecture
What is the architecture of the Synchronous FIFOs? Is the memory managed by pointers or shifting registers? If the fullness of the FIFO is managed well, is it possible to endlessly read and write?
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Not yet rated
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06/17/11 |
Usage of different speed grades in synchronous FIFOs
- Can I replace a -35 device with with a -25 device?
- If the two ports of my FIFO are running at different rates, how do I pick a speed grade for my system?
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Not yet rated
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06/17/11 |
Driving REN1 and REN2 together for some families of synchronous FIFO's
- Can I drive /REN1 and /REN2 with the same signal?
- Can I tie Read Enable 1 and Read Enable 2 together?
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Not yet rated
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06/17/11 |
Retransmit feature of synchronous FIFO's
- What happens to the data lines when RT is pulsed and during the tRTR time?
- Can a selected block of data be retransmitted?
- What considerations are there for using the retransmit operation?
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Not yet rated
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06/17/11 |
Delay buffers using synchronous FIFOs
How can I make a delay buffer that always has x number of words in the buffer?
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Not yet rated
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06/17/11 |
Synchronous FIFO Clocks
- Are there any requirements for clock duty cycles?
- Do the clocks have to have 50 percent duty cycles?
- What are the requirements for the clock driving sync FIFOs?
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Not yet rated
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06/17/11 |
Output State for the FIFOs
- Can I make the data outputs (Q0 - Q8) to be normally high?
- What is the status of the data outputs after reset?
- What happens to the data outputs when /OE is asserted?
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Not yet rated
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06/17/11 |
Driving 3.3V I/Os on a 5V device
- Can I drive 3.3V I/Os into a 5V part?
- What are the minimum input levels for 5V devices?
- Will my 3.3V processor be strong enough to connect to a 5V device?
- Will a -1V undershoot on the inputs cause problems?
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Not yet rated
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06/17/11 |
Usage of XI#, XO#, and FL#/RT signals
- What should pin XOn, /XO, RXOn, /RXO, RXIn, /RXI, WXOn, /WXO, WXIn, /WXI, FLn, /FL be tied to if I am not cascading?
- What should these pins be tied to if I am width cascading?
- What should these pins be tied to if I am depth cascading?
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Not yet rated
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06/17/11 |
Maximum number of cascaded FIFOs
How many FIFOs can I cascade in depth and by width? What are the considerations?
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Not yet rated
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06/17/11 |
Using a FIFO as a transparent device
- Can the FIFO be used transparently?
- Can data written into the FIFO be read straight out?
- Can one tie WCLK and RCLK together?
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Not yet rated
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06/17/11 |
CY3267, CY3268 OCD and EEPROM issues
The below two issues are encountered with the CY3267/CY3268:
1.While trying to connect to the debugger , the error message “Attached pod (00bf0022) is not compatible with the selected PSoC” is thrown.
2.While writing to the EEPROM using the E2PROM module, the API 'E2PROM_bE2Write' returns a value of ‘-1’ indicating write failure.
Why is this so and what is the solution?
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Not yet rated
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06/17/11 |
CY3269N - Low Battery Functionality
What should I do if the HBLED on CY3269N flickers and stays off even though the board seems to be powered on (D3 – Red LED is ON)?
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Not yet rated
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06/17/11 |
CY3267 PowerPSoC Lighting Evaluation Kit - GUI Known Issues and Workarounds
CY3267 - Intelligent Lighting Control 64-bit OS Support, Unhandled Exception and Communication Break
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Not yet rated
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06/17/11 |
Asserting the PKTEND strobe
When operating in slave FIFO mode, can the external master assert the packet-end pin on the same rising edge of IFCLK when the last write into the FIFO occurs?
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Not yet rated
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06/17/11 |
Purpose of the SLCS# pin of the CY7C68013 (FX2)?
What is the purpose of the SLCS pin. Do I have to use this pin for interfacing/accessing the endpoint FIFOs?
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Not yet rated
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06/17/11 |
Timing specification between SLOE and SLRD in EZ-USB FX2
There are no timing restrictions between SLRD and SLOE specified in the FX2 datasheet. Can you please clarify what is the timing requirement between SLOE and SLRD for FIFO read in synchronous and asynchronous mode?
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Not yet rated
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06/17/11 |
Example on Slave FIFO for FX2
Do you have any examples of the Slave FIFO Interface on the FX2?
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Not yet rated
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06/17/11 |
Driving IFCLK on the CY7C68013
Does IFCLK need to be driven continuously, or only when the SLxx pin is set LOW?
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Not yet rated
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06/17/11 |
Handling Odd Count Packet Sizes Between an FX2-SX2 16-bit WORDWIDE Interface
When an odd number of bytes (eg. 45 bytes) are sent from FX2's EP2OUT to SX2's EP6IN, the SX2 receives it in word form and it is considered 23 words, since we are using a 16-bit WORDWIDE interface across the two chips.
When the words are converted back to bytes later, the SX2 will multiply it by 2 and becomes 46 bytes in the endpoint FIFO instead of the original 45 bytes originally sent. What should be done to ensure that the byte count in SX2 is 45 bytes in this case?
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Not yet rated
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06/17/11 |
Setting Polarity for FIFO Programmable-level Flag (PF) on the FX2 (FX2 - BHA)
How do I set polarity for FIFO programmable-level flag (PF)?
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Not yet rated
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06/17/11 |
Physical Interconnect Between External Master and FX2 Slave FIFO Interface
I would like an example physical interconnect between our external master and the FX2's Slave FIFO Interface. Where can I find one?
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Not yet rated
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06/17/11 |
Do I Need to Monitor the FIFO Flag Status When Using the FX2 as a Slave for Payload Data?
If I am primarily using FX2 in Slave FIFO mode as a conduit for payload data, do I need to monitor the status of FIFO flags?
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Not yet rated
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06/17/11 |