|
Title
|
Customer Rating
|
Updated
|
Trip Voltage and EEPROM Access of ISD-300A1
What is the POR trip voltage and time to first EEPROM access for the ISD-300A1?
|
Not yet rated
|
06/19/11 |
INTRQ Support by ISD-300
Does the ISD-300 support INTRQ (ATA interrupt request)?
|
Not yet rated
|
06/19/11 |
USB SmartCable Drivers for ISD-300
Where to find drivers for a USB SmartCable used with an ISD-300?
|
Not yet rated
|
06/19/11 |
Theta Ja for CY2304
What is theta Ja for CY2304?
|
Not yet rated
|
06/19/11 |
Multiple Modes Enabled in ISD-300A1
I have both ATA/ATAPI UDMA and "Override PIO Mode" enabled in the EEPROM data. Which configuration will be used?
|
Not yet rated
|
06/19/11 |
"Object Error" in Designer
When I open PSoC Designer I get an error message "object error " (see object_error.jpeg)
|
(1/5) by 1
user
|
06/19/11 |
'Static' local variables do not show-up automatically in the 'Locals' window
When using the debugger in PSoC Designer, local variables that are declared 'static' should show-up automatically in the 'Locals' window. But they do not. How to fix it?
|
Not yet rated
|
06/19/11 |
bInterfaceSubClass Set to 0x06 on the ISD-300A1
Is there any problem if bInterfaceSubClass is set to 0x06 (SCSI pass-through)?
|
Not yet rated
|
06/19/11 |
CY23S09 Behaviour in PLL Bypass Mode
Why there is no output when using the CY23S09 in PLL bypass mode, S2 = 1 and S1 = 0?
|
Not yet rated
|
06/19/11 |
Theta JC of CY2308
What is theta JC for CY2308?
|
Not yet rated
|
06/19/11 |
IE script error pops up whenever any project or workspace is opened
Whenever any project or workspace is opened in PSoC Designer, it gives IE script error " 'g_SvgDoc.rootElement' is null or not an object ". How to fix it?
|
Not yet rated
|
06/19/11 |
Unhandled exception error on opening project with PSoC Creator
How to resolve the unhandled exception error when open a project with PSoC Creator?
|
Not yet rated
|
06/19/11 |
CY3240-I2C-USB Bridge used to program PSoC device.
Can I use the CY3240 I2C-USB Bridge to program a PSoC?
|
Not yet rated
|
06/19/11 |
Replacement for W194-70G
The obsolete data sheet for W194-70G canot be found, is there a cross reference?
|
Not yet rated
|
06/19/11 |
CY2308-2 Outputs Inverted in Bypass Mode.
Why is the output of the CY2308-2 inverted in bypass mode?
|
Not yet rated
|
06/19/11 |
Reading the Interrupt Status Byte of the SX2
What register should the external master address in order to read the contents of the Interrupt Status Byte?
|
Not yet rated
|
06/19/11 |
SX2 device displayed as an 'Unknown device' on device manager.
While using the default SX2 descriptors as provided in section 12.0 of REV D version of the datasheet and the VID/PID reported in the device descriptor bound to the ezusb.sys driver (via the ezusbw2k.inf file). When the device is plugged in, it fails to enumerate and shows up as an "Unknown device" in the device manager. What could be the problem?
|
Not yet rated
|
06/19/11 |
RESET vs. CLK (CY7C68000).
Is there a way to keep the CLK output running when the RESET input is asserted? If not, what is the maximum time from the de-assertion of RESET until the CLK output is stable again?
|
Not yet rated
|
06/19/11 |
Reference design for CY7C68003 TX2UL
Does Cypress provide a reference design on how to drive the UTMI interface?
|
Not yet rated
|
06/19/11 |
Thermal pad specification for the TX2 QFN package
What is the thermal pad specification for the TX2 QFN package?
|
Not yet rated
|
06/19/11 |
Electrostatic Discharge Protection for CY7C68000
What does Cypress recommend for electrostatic discharge protection of the CY7C68000 part?
|
Not yet rated
|
06/19/11 |
Differences between the CY7C68000 and the CY7C68000A
What is the difference between the CY7C68000 and the CY7C68000A?
|
Not yet rated
|
06/19/11 |
CY7C68001 Operation Without an On-board CPU
Can the CY7C68001 operate an application without an onboard CPU?
|
Not yet rated
|
06/19/11 |
SX2 reset time and recommeded circuit
What is a good reset time for the SX2? How should the RESET be wired?
|
Not yet rated
|
06/19/11 |
Connecting SX2 SLOE and SLRD together
Can the two signals SLRD and SLOE specified in REVD version of the SX2 datasheet be tied together as there is no timing restriction between them.
|
Not yet rated
|
06/19/11 |
Reprogramming the CY24LC64 EEPROM on the SX2
How to reprogram the CY24LC64 EEPROM on the SX2 development kit board?
|
Not yet rated
|
06/19/11 |
Reading GPIO inputs
|
Not yet rated
|
06/19/11 |
SRAM to FX2LP for Memory Expansion
How can I wire an SRAM to the FX2LP device for memory expansion. Please provide a pin to pin connection detail.
|
Not yet rated
|
06/19/11 |
Bad Duty Cycle Fix Possibility by ZDB
Can a ZDB fix bad duty cycle?
|
Not yet rated
|
06/19/11 |
EPPROM Programming Software -- ISD-300A1
Is there software available to program the EEPROM for the ISD-300?
|
Not yet rated
|
06/19/11 |
Asserting PKTEND pin when endpoint buffer is full in FX1/FX2/FX2LP
There is a note in the technical reference that states to never assert PKTEND on a full FIFO. If I have a quad buffered system and I put the last byte into the last packet, causing FULL flag to assert (operating in manual mode) can I not assert PKTEND commit the 4th packet to USB?
|
Not yet rated
|
06/19/11 |
Single-Ended PECL
Can PECL inputs be driven single-ended?
|
Not yet rated
|
06/19/11 |
Static Discharge Voltage Test
What is the test that is used to screen Static Discharge voltage?
|
Not yet rated
|
06/19/11 |
Precautions when handling Op-Amp dedicated pins in a PSoC 3/5 design
What are the precautions to be taken when handling Op-Amp dedicated pins in a PSoC 3/5 design?
|
Not yet rated
|
06/18/11 |
Burst and NoBL SRAM access
What do you mean by 2-1-1-1 and 3-1-1-1 accesses which you show for Sync Burst and NoBL SRAMs?
|
Not yet rated
|
06/18/11 |
Simultaneous Reads and Writes on the CY7C1302 QDR
On the QDR SRAM, can I give a READ and WRITE command simultaneously?
|
Not yet rated
|
06/18/11 |
JTAG pins floating
If we do not want to use the JTAG, can we leave those pins floating?
|
Not yet rated
|
06/18/11 |
Capturing data with a single clock using DDR SRAMs
I am using a FPGA with a DDR interface that will support capturing data off both edges of a single clock. Can I use only one of the CQ and CQ* pairs and capture both edges?
|
Not yet rated
|
06/18/11 |
Effect of Speed, Package Type and Die Revisions on Models
When browsing the website for SRAM models, I have noticed that certain speeds have the same models while other models are package or revision specific. How do you know which models are affected by revisions, packages, or speed of the device.
|
Not yet rated
|
06/18/11 |
K and K\ signals in DDR
Are K, K\ are differential signals in DDR?
|
Not yet rated
|
06/18/11 |
Standby current when address lines are float
Does floating address lines in the standby mode have any effect on the standby current of the device?
|
Not yet rated
|
06/18/11 |
NoBL SRAM CY7C1370DV25 JTAG test
The NoBL SRAM CY7C1370DV25 issue list indicates that the part does not support boundary scan. Can I still run the boundary scan / JTAG test on a system which has this memory?
|
Not yet rated
|
06/18/11 |
Termination design on the Sync SRAM NoBL
What is the recommendation for the termination design for the Standard Synchronous/ NoBL SRAMs ?
|
Not yet rated
|
06/18/11 |
Number of cycles required to read CY7C1380 (standard Sync pipeline)
Is it possible to do an ARBITRARY NUMBER of CONSECUTIVE read access (one access per clock cycle) to a series of random locations; i.e. it is possible to use this chip to read the entire memory in 512K clock cycles?
|
Not yet rated
|
06/18/11 |
Parity generation during Read and Write
How is parity generated during reads and write?
|
(4/5) by 1
user
|
06/18/11 |
TDO Output of the JTAG circuitry
When Boundary Scan input signals are applied to TDI, TCK and TMS pins of the chip, no output signal can be detected from TDO pin of the chip. What is the problem?
|
Not yet rated
|
06/18/11 |
Clock enable CEN# reduces power consumption if disabled
Does Clock enable CEN# reduce power consumption if disabled (High)?
|
Not yet rated
|
06/18/11 |
SRAM load Conditions for given specs
What is the load to which the datasheet parameters are guaranteed for?
|
Not yet rated
|
06/18/11 |
necessity of clock when a ZZ pin is asserted
According to the datasheet for a Sync SRAM device, the clock is still available to the device after the asynchronous ZZ signal is asserted. Is the clock necessary? Is it possible to stop applying the clock, by tying the clock to either "1" or "0", after asserting the ZZ signal?
|
Not yet rated
|
06/18/11 |
SRAM Interface to Motorola 7410 Processor
What are the ranges of densities that can be used for L2 Cache application with a Motorola 7410 Processor?
|
Not yet rated
|
06/18/11 |