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Title
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Customer Rating
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Updated
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SMPTE standards supported by HOTLink family
1)How can I use the HOTLink1 parts in a SMPTE-259M application?
2)Does Cypress have a part that supports the SMPTE 310M video standard?
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(4/5) by 2
users
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07/01/11 |
EZHOST/OTG development environment for CY7C68013A
Can the EZHOST/OTG development environment be used to develop firmware for CY7C68013A ?
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Not yet rated
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07/01/11 |
AT2LP Pull-Down resistor of DD7 port
According to AT2LP datasheet, 1K ohm pull-down resistor is required on DD7 pin. Why the pull-down is needed?
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(5/5) by 1
user
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07/01/11 |
Obsolescence of 56 QFN (8x8x1.0mm) punch singulation products in FX1/FX2LP family
Is CY7C68014A-56LFXC obsolete? What is the drop-in-replacement? Are all parts in FX2LP family in the same package obsolete?
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(4.3/5) by 4
users
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07/01/11 |
Explanation of ECC (error correction code) implementation in EZ-USB for data that passes through its GPIF (general programmable interface)
Explanation of ECC (error correction code) implementation in EZ-USB for data that passes through its GPIF (general programmable interface)
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Not yet rated
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07/01/11 |
Firmware Download through CyConsole or Control Centre
It is observed every time that when a hex file or a .iic file is getting downloaded by the CyConsole or the Control Centre, some hex data is being written into the chip before the correct hex file is written. What is the explanation for this procedure?
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(3/5) by 1
user
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07/01/11 |
Byte Count Register For FX2 FIFOs
How do I read the number of bytes in a FIFO when FX2LP is operating in AUTO OUT mode?
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Not yet rated
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07/01/11 |
IFCLK (internal/external) - Design aspects to considers
What are the design aspects that need to be considered when using IFCLK (internal/external)
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Not yet rated
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07/01/11 |
Should I use HOTLink CY7C924ADX or CY7C9689A
Should I use HOTLink CY7C924ADX or CY7C9689A?
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Not yet rated
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07/01/11 |
Loading Code into External Code Memory (ROM)
What is required to load code into a external code memory chip(ROM) that is attached to the CY7C68013A?
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Not yet rated
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07/01/11 |
EP1 Buffer Reset
Is it possible to reset the EP1 buffers the same way as with the other EP buffers (2,4,6 and 8)?
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Not yet rated
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07/01/11 |
NX2LP Flex Kit Enumeration
Why doesn’t the NX2LP Flex kit, without a NAND Flash, enumerate as a mass storage device when the CY3686FW is downloaded onto its RAM?
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Not yet rated
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07/01/11 |
Controlling LEDs on FX2LP board
How to light LED's on the FX2LP board from the code to have software test points?
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Not yet rated
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07/01/11 |
Plug n Play Detection when using CYAPI.lib
How can we implement hot-plugging detection when using cyapi.lib?
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(5/5) by 1
user
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07/01/11 |
Device not working properly with Ezloader driver
My device is not working properly when bound to the driver created using Ezloader method. What might be the reason?
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(4/5) by 1
user
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07/01/11 |
Configuration of the Status In (SI) and Status Out (SO) Pins
1) If I want to use the SO pin as a true output of SI, but the signal it is connected to is pulled up to Vcc during startup, will this affect the configuration of SO?
2) Can I change the state of SO is used during operation?
3) How is the function of the INB(INB+) input and the SI(INB-) input defined?
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Not yet rated
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07/01/11 |
CYAPI - Detect if some other application is using the USB device
How do I detect using the CYAPI library, if some other application is already using my USB device?
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Not yet rated
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07/01/11 |
Failed to set data to Verbose error in CyConsole
When I run CyConsole in non-administrator user I get an error message ?Failed to set data to Verbose?. How to solve this issue?
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Not yet rated
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07/01/11 |
Values of Members like Target, ReqType, Direction, ReqCode, Value and Index from ControlEndPt
In CyAPI.lib, to use methods like XferData(), it requires to configure the members like Target, ReqType, Direction, ReqCode, Value and Index from ControlEndPt (instance of CCyControlEndPoint). Where can I find the information of these members?
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Not yet rated
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07/01/11 |
Can the FIFO be bypassed in CY7C924ADX when using the byte-packer
Can I bypass the FIFO in CY7C924ADX when I want to use 10-bit encoded mode?
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Not yet rated
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07/01/11 |
FX2LP Audio Device in windows volume control
How to Get FX2LP Audio Device to Appear in Windows Volume Control?
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Not yet rated
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07/01/11 |
Error: File type mismatch. Attemted to put code in a codeless PROM type
When I am using 0xC0 as first byte in Hex2bix utility to generate .IIC file it gives this error: "Error: File type mismatch. Attempted to put code in a codeless PROM type."
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Not yet rated
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07/01/11 |
CY7C68013A - RESERVED pin
What should be done with the RESERVED pin #21 of 56-pin CY7C68013A?
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(5/5) by 2
users
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07/01/11 |
AT2LP has a slower HDD format time than CY7C68300A
Why AT2LP has a slower HDD format time than CY7C68300A?
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(5/5) by 1
user
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07/01/11 |
FX2LP - Difference between Port I/O, GPIF and Slave FIFO
What are the key differences between the three modes: PORT, GPIF, FIFO. Once selected you can't really switch between the three can you?
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Not yet rated
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07/01/11 |
Address line configuration setting in GPIF Designer
I am using the GPIF Designer. I use PE7 for another hardware function . I have 'right-clicked' in the Block Diagram tab and cleared the ADR8 box (the line went grey). But when I look at the gpif.c file generated I see:
// Configure GPIF Address pins, output initial value,
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
OEC = 0xFF; // and as outputs
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
OEE |= 0x80; // and as output
This seems to be setting PE7 as an output (I need it as an input). I can obviously manually edit gpif.c, but if someone modifies the design later and regenerates gpif.c this will cause a problem.
Is there a way to stop GPIF Designer from affecting PE7?
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Not yet rated
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07/01/11 |
HID example for FX2 (CY7C68013)
Can I get the HID example for FX2 (CY7C68013)?
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(5/5) by 2
users
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07/01/11 |
Clarification on FX2 FIFO Full Flag behavior on OUTs
The FX2 is setup with a 512 byte, quad buffered, OUT endpoint. Would the FIFO full flags go active once a 512 byte packet is received from the host, or after 4 x 512 bytes are received from the host?
An experiment with a double buffered (2x512) EP2 was done, where 2 one-byte packets were sent to it over USB. The full flag did not assert until the second byte had been placed into the second 512-byte buffer and passed to the slave side. Is this the correct behavior?
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Not yet rated
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06/30/11 |
LUN0 and LUN1 String Format
How to display the USB device name in Device Manager and the Properties windows?
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Not yet rated
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06/30/11 |
Voh of 2.4V Minimum with a 3.3V Supply (CY2292F)
Why does Cypress specify a Voh of 2.4 v min with a 3.3v supply when in fact the measurement shows a voltage exceeding 0.95 vcc (close to 3.3 v)? This device is to be used to drive a clock pin that requires the CMOS range not, the TTL 2.4 v range of level for the logic high.)
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Not yet rated
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06/30/11 |
Algorithm For Calculating P & Q values
How can I calculate optimal P and Q counter values for the CY22150 without using CyberClocks?
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Not yet rated
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06/29/11 |
Serial Programming PLL1 Frequency Changes In The CY22393/4/5
How can I serially program frequency changes into PLL1 of the CY22393/4/5?
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Not yet rated
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06/29/11 |
Changing The Default SPI Address
What is the low-level SPI procedure for changing the default address from 69H to another value?
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Not yet rated
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06/29/11 |
Output Voltage Range Possibility for CY22800
How can a varying output voltage of 1 to 5.5 volts be implemented?
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Not yet rated
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06/29/11 |
CY22381 Frequency Ranges
What are the minimum and maximum frequency ranges for the CY22381?
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Not yet rated
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06/29/11 |
CY22394 Frequency Ranges
What are the minimum and maximum frequency ranges for the CY22394?
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Not yet rated
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06/29/11 |
Crystal Drive Level for The CY22050.
What is the crystal drive level is for the CY22050 clock generator?
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Not yet rated
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06/29/11 |
Eight Different Values Programming Possibility in CY22394
It is possible in the CY22394 to select eight different values of the frequency of PLL 1 using the start-up values of S0, S1 and S2. However, is it possible to program them to flash using software?
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Not yet rated
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06/29/11 |
CY22393 Frequency Array Table: 8x3 registers Register Requirement
Why does the SONOS Frequency Array Table of part CY22393 include 8x3 registers for the configuration of the PLL1 (40h to 57h) when S2 has only 2 bits? The 4x3 registers seem to be sufficient (40h to 4Bh).
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Not yet rated
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06/29/11 |
Jitter Specification of the CY22800FXC
We have different configurations so what is the typical ans maximum jitter?
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Not yet rated
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06/29/11 |
Crystal Specifications for the CY22381
What are the specifications that should be looked at when we select a crystal of a particular frequency we need for CY22381?
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Not yet rated
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06/29/11 |
Serial Programming Sequence in CY22393/4/5
What is the programming protocol or sequence for the CY22393/4/5?
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Not yet rated
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06/29/11 |
Default Device Address in CY22393/4/5
What is the default device address for serial programming of CY22393/4/5 devices?
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Not yet rated
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06/29/11 |
Programming the CY22150 with FPGA
When using an FPGA on a PCB for serial programming of the CY22150, during write mode, the device will respond with an ACK pulse after eight bits by pulling the SDAT line low. Is this a 'weak 0', or a 'strong 0'? Can there be a conflict with the I/O of the FPGA?
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Not yet rated
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06/29/11 |
Skew from External Clock with CY22381
What is the skew of the output from an external input clock with the CY22381?
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Not yet rated
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06/29/11 |
Need for Different Checksums for CY2292 JEDEC Files
Why are there different checksums for JEDEC files on the CY2292F?
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Not yet rated
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06/29/11 |
Validity of Input Frequency Change without Jedec File Change for CY25100
Can we change the reference frequency without reprogramming the CY25100?
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Not yet rated
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06/29/11 |
External Crystal Load Capacitor Requirement for the CY22381
Can we have external load capacitors while using a crystal as a reference input for the CY22381?
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Not yet rated
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06/29/11 |
Programming Tools Options for the CY22801
What are the programming tools available for programming the CY22801?
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Not yet rated
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06/29/11 |
Possibility of CY22801 as a Zero Delay Buffer (ZDB)
Can the CY22801 maintain the phase between the input and the output and act as a Zero Delay Buffer?
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Not yet rated
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06/29/11 |