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Title
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Customer Rating
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Updated
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Default I2C slave address of CY8C20110
What is the default I2C slave address of any CapSense Express device?
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Not yet rated
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03/28/11 |
First Touch Kit - Compatibility with Windows Vista x64
My PC running with 64 bit Windows Vista does not detect the Psoc First Touch kit as a USB device. How can I solve this problem?
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Not yet rated
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03/28/11 |
Clock setting for UART Baud Rate
How to configure the baud rate for UART/TX8/RX8 User Module in PSoC1?
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Not yet rated
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03/28/11 |
Getting an Analog User Module to work
What are the basic necessities of an Analog Block to work properly in PSoC1 ?
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Not yet rated
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03/28/11 |
Effect of using P2[4] for digital signals on AGND
What is the effect of using P2[4] for digital signals on AGND on PSoC 1?
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Not yet rated
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03/28/11 |
Changing MUX Values
How do I Change the Second Level MUX or ACol1mux Value?
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Not yet rated
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03/28/11 |
Avoiding the Dummy Byte When IrDA Rx is Started
I always get the byte 0xFF on IrDA Rx start. How can I avoid it ?
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Not yet rated
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03/28/11 |
DAC on a CY8C21x34
How do I configure an SC Block as a DAC in CY8C21x34 as there is no option of configuring ASE type switch capacitor blocks as DACs ?
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Not yet rated
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03/28/11 |
FX2LP Bulk OUT Transfer Followed by Bulk IN Transfer
Can FX2LP perform a Bulk OUT transfer, and immediately after it has completed, follow with a Bulk IN operation? Is a provision necessary for some kind of handshaking between FX2LP and the host so as to ensure proper operation in this case?
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Not yet rated
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03/28/11 |
Bulk Tansfers Using FX2/FX2LP
Is there any reason for the IOCTL_EZUSB_BULK_READ, used in the ezusb.sys general purpose driver to transfer blocks less than or equal to 64K each time? If I want to transfer, say, 2 MB in just one call, what changes would I have to make in the driver source code (ezusbsys.c) in order to make it work?
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(4/5) by 1
user
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03/28/11 |
CY7C68300 / CY7C68300A - AT2 Configuration through EEPROM
How can the configuration information in the EEPROM be modified for the AT2?
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Not yet rated
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03/28/11 |
CY7C68300 - Putting AT2 into Suspend.
How to get the AT2 go into a suspend mode without the USB bus (CY7C68300 silicon only)?
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Not yet rated
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03/28/11 |
Maximizing Transfer Rate with the FX2/FX2LP
What is the maximum USB throughput achievable with EZ-USB FX2/FX2LP?
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Not yet rated
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03/28/11 |
BULK TRANSFER Rate with CY7C68013
Can we guarantee 4 512 bytes packets per microframe data rate for bulk transfer mode through proper register settings?
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Not yet rated
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03/28/11 |
R/B pins for the CY7C68023
What is the functionality of multiple R/B pins in CY7C68023?
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Not yet rated
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03/28/11 |
EEPROM Compatibility for AT2
Does the CY7C68300A use the same EEPROM as the CY7C68300?
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Not yet rated
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03/28/11 |
EPxPING Interrupt in FX2LP
What is a EPxPING Interrupt?
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Not yet rated
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03/28/11 |
CY7C68300 / CY7C68300A -- ATA_ENABLE Line
Is it possible to use the ATA_ENABLE line to pause access to the ATA bus at any time - including during a data transfer?
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Not yet rated
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03/28/11 |
Changing the polarity of programmable flag
Is there a way to change the polarity of the Programmable Flag (PF) ?
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Not yet rated
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03/28/11 |
SX2 as composite device
Is it possible to create a HID keyboard, Hid mouse, and a HID proprietary device using a single SX2 device (cy7c68001)?
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Not yet rated
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03/28/11 |
Usage of CPUCS register to reset the 8051 core in FX1/FX2/FX2LP
In FX1/FX2/FX2LP, can the firmware reset the 8051 core by setting the bit 0 of CPUCS register?
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Not yet rated
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03/28/11 |
Roxio Toast Support for AT2 in Mac OS
Does Toast support AT2?
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Not yet rated
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03/28/11 |
More than one data transfer in one GPIF waveform of the FX1/FX2/FX2LP
Can I read or write two bytes (if WORDWIDE=0) or words (if WORDWIDE=1) in one waveform?
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Not yet rated
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03/28/11 |
CY7C68300 / CY7C68300A -- ATA polling.
Can the AT2 be set to polling mode, rather than relying on the ATA IRQ signal?
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Not yet rated
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03/28/11 |
Differences with ATA_EN between the AT2 and AT2+
Are there any differences with ATA_EN between the AT2 and AT2+?
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Not yet rated
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03/28/11 |
AT2 for an USB2.0 compact flash card reader
Can (CY7C68300A) AT2 be implemented for an USB2.0 compact flash card reader?
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Not yet rated
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03/28/11 |
Changing the GPIF Waveform Descriptors for the EZ-USB FX2/FX2LP (CY7C68013 /CY7C68013A) On the Fly
What should I be aware of when changing the GPIF waveform descriptors in the middle of a GPIF transfer?
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Not yet rated
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03/28/11 |
Writing data into the dual-port
- After the data is clocked into the sync DPRAM, on which clock is the data actually written to the memory?
- How long does it take for data written into the dual-port to be accessible?
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Not yet rated
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03/27/11 |
Read data problems in synchronous dual-ports
Why is the data read from a synchronous dual-port always the last word written even though the read address is different than the write address?
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Not yet rated
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03/27/11 |
Generation of FIFO empty and full flags
How are FIFO empty and full flags generated?
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Not yet rated
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03/27/11 |
Pulling multiple I/Os to Vcc through only 1 pull up resistor
Is it fine to pull up (or down) multiple signals through only 1 resistor?
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Not yet rated
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03/27/11 |
Unused I/Os for Dual port SRAM's
- What should I do with the unused I/O pins?
- Can unused I/Os be tied to each other if the relevent byte enable is disabled?
- What should I do if my processor is only 32 bits wide and the data bus is 36 bits wide?
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(4/5) by 1
user
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03/27/11 |
Creating a FIFO using a synchronous burst dual-port RAM
- Can I use a dual-port as a FIFO?
- If I am using the burst mode of a dual-port to create a FIFO, what should I do with the address lines?
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Not yet rated
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03/27/11 |
Clearing the mailbox interrupt
- How to clear the interrupt signal ?
- How to use the mailbox feature?
- What is min value of time when an interrupt is observed to the time when the interrupt is cleared?
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Not yet rated
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03/27/11 |
Output Enable (OE) signal behavior
Is OE# an asynchronous or synchronous input?
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Not yet rated
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03/27/11 |
Flow-through vs. Pipelined memory
- What is the difference between FT and PL modes?
- Which mode should I use?
- Why are newer dual-ports pipelined only?
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Not yet rated
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03/27/11 |
Arbitration code for Dual port SRAMs when accessed from both sides
- Since there is no guarantee as to what data is read during simulatneous access, can I control that with logic?
- Do you have anything to help prevent corrupting of data when trying to write to the same location at the same time?
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Not yet rated
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03/27/11 |
Difference between CY14B101L and Simtek part STK14CA8
What is difference between CY14B101L and Simtek part STK14CA8 ?
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(5/5) by 1
user
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03/27/11 |
Replacing a CY7C14X slave device with a CY7C13X master device
For a Dual port SRAM, Can I replace a slave device with a master device? What are the differences between the slave devices and master devices? - Can I use only master devices?
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Not yet rated
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03/27/11 |
Replacing obsolete asynchronous dual-port RAMs
The part I was using is now obsolete. What is a good replacement part?
Is there something I can use to replace this asynchronous dual-port?
What is important when picking a replacement asynchronous dual-port?
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Not yet rated
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03/27/11 |
Write Operation Timing of Asynchronous Dual-ports
- When is the internal logic of an asynchronous dual-port latch the address during a write cycle?
- Is the address latched when CE# transitions to low?
- Do write operations begin when R/W# transitions to low or when CE# and R/W# both transition to low?
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Not yet rated
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03/27/11 |
Comparision between Asynchronous and Synchronous Dual-Port RAMs
- What are the main differences between Asynchronous and Synchronous dual-port rams?
- What are the advantages and disadvantages of using either one of them?
- Under which circumstances is it better to use Async/Sync?
- Should I use asynchronous or synchronous dual-ports for my application?
- I have a fast processor. Should I use a synchronous or asynchronous dual-port?
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Not yet rated
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03/27/11 |
Default Stae of GDx and PWx Pins at Power Op or Reset - CY8CLED04D01
What is the default state of GDx and PWx pins of CY8CLED04D01 at power up or during reset?
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Not yet rated
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03/27/11 |
Change CPU Clock of PSoC in Firmware
How to change the CPU_Clock of the PSoC in the firmware (for example switch between Sysclk/2 and Sysclk/1) ?
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Not yet rated
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03/27/11 |
Glitch on P1[0] at POR and XRES
After POR or XRES event, P1[0] goes high for some time. Why is it so?
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Not yet rated
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03/27/11 |
Digital Input Row Synchronizers
Why the accuracy of Digital block in PSoC1 does not improve even when an accurate external clock is selected?
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Not yet rated
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03/27/11 |
Use of MiniProg3 to program PSoC1 parts
Can Miniprog3 be used to program PSoC1 devices?
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Not yet rated
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03/27/11 |
Difference between Bank 0 and Bank 1 registers
What is the difference between Bank 0 registers (User space registers) and Bank 1 registers(Configuration space registers)?
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Not yet rated
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03/27/11 |
Analog Column clock for 3-OpAmp topology Instrumentation Amplifier
Does the analog column clock has an effect on the output of 3-OpAmp topology Instrumentation Amplifier?
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Not yet rated
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03/27/11 |
Allocation of Variables at Absolute Address in RAM
How do I allocate variables at absolute address in RAM?
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(5/5) by 1
user
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03/27/11 |