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Title
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Customer Rating
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Updated
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status of pins while using CY62157EV as 1Mx8 or 512Kx16
What should be the state of the pins while using CY62157EV30LL as 1Mx8 or 512Kx16
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Not yet rated
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04/04/11 |
Qualification Report (QTP)
How do I find a Qualification Report for a particular device?
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Not yet rated
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04/04/11 |
Command Register Write Delays With CY7C68001.
Is the maximum delay between writes to command registers 200ns? If the delay is enforced, will the READY line come out of the SX2?
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Not yet rated
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04/04/11 |
Identifying data written from host to SX2 using FLAGS bit
How to know when the host has written some data to the device?
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Not yet rated
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04/04/11 |
Low speed support for SX2
Does the SX2 support Low-speed (1.5 MBps)? Are there other Cypress devices that only provide support?
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Not yet rated
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04/04/11 |
Default.nx2 file contents of CY3686
What does the default.nx2 file contain?
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Not yet rated
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04/04/11 |
Alternate functions of Port E bit[2:0] or PE[2:0]
What are the alternate functions of port E bit[2:0] or PE[2:0] ?
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Not yet rated
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04/04/11 |
GIR - ATA commands supported by the AT2+ (CY7C68300A)
Is there a list of ATA commands that the AT2+ (CY7C68300A) can send to a device?
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Not yet rated
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04/04/11 |
Details of APIs available in EZUSB.LIB file
Where can I find the details about the APIs available in the EZUSB.LIB?
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Not yet rated
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04/04/11 |
Location of FX2 Board Schematic
Where can I get the EZ-USB FX2 Development Board schematic (pdf and Orcad files)?
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Not yet rated
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04/04/11 |
FX2LP (CY7C68013A) Errata Document
Where can I find the errata document for EZ-USB FX2LP (CY7C68013A)?
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Not yet rated
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04/04/11 |
Enabling External Interrupts in FX2LP
How to enable to external interrupts in FX2LP?
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Not yet rated
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04/04/11 |
SFR's associated with serial ports in FX2LP
What are the SFR's associated with serial ports in FX2LP?
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Not yet rated
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04/04/11 |
Uvision Debugger: Can't debug with USB to RS232 adapter
Does the debugger work with a USB-to-RS232 adapter?
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Not yet rated
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04/04/11 |
Wear leveling algorithm used in NX2LP
What is the wear leveling algorithm used in the NX2LP?
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Not yet rated
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04/04/11 |
EZLOADER Firmware Download Procedures
What is the basic procedure that the ezloader driver uses to download firmware to the EZ-USB FX2 device?
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Not yet rated
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04/04/11 |
Full Flag De-assertion in FIFOs of FX2LP
When is Full Flag de-asserted? Is it after one byte/word is sent to PC or after the entire FIFO bytes/words are sent to PC?
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Not yet rated
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04/04/11 |
Empty Flag De-assertion in FIFOs of FX2LP
When is EMPTY Flag deasserted? Is it after one byte/word is in the FIFO or After the entire FIFO is filled up?
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Not yet rated
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04/04/11 |
AT2LP setup time
How much time is necessary before the AT2LP can communicate with the ATAPI device once the power supply is turned on?
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Not yet rated
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04/04/11 |
Single Chip NAND Flash interfacing/Hub possibility
Is it possible to have a single chip solution for a device that acts as a mass storage device as well as a hub?
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Not yet rated
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04/04/11 |
Turning On the GSTATE[2:0] Signals for Debugging the GPIF State Machine in EZ-USB FX2/FX2LP
For the EZ-USB FX2/FX2LP, how do I turn on the GSTATE[2:0] signals for debugging the GPIF state machine? Which pins are used for GSTATE[2:0]?
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Not yet rated
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04/04/11 |
Lack of Line Impedance Matching Resistors in FX2 Reference Designs
The FX2 (CY7C68013) reference designs do not show the normal line impedance matching resistors. Also, the manual does not reference them on the host attachment resistor of 1.5 K ohms. What should be the proper values for the FX2?
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Not yet rated
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04/04/11 |
Tri-stating the IDE bus on the CY4611
Can the 8051 tri-state the ATA interface pins on the CY7C68013 Mass Storage application (Reference design CY4611) so that another device can take over the bus?
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Not yet rated
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04/04/11 |
USB to ATAPI Boot Support Under DOS With CY7C68013 FX2.
What is the procedure to boot a DOS system directly from the USB hard disk via 68013/68300 mass storage reference. Is it Ok to boot under USB-HDD setting from AMI BIOS [The BIOS cannot find the hard disk through USB (68013) using the CY4611 evaluation board] ?
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Not yet rated
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04/04/11 |
Signal Buffering on the FX2 ATA Reference Design CY4611.
The ATA signals going off the board are not buffered in the FX2 reference design CY4611. Is this OK in terms of drive and protection?
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Not yet rated
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04/04/11 |
Working of ATA_EN on the CY4611 reference design
How does ATA_EN work on the CY4611 reference design?
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Not yet rated
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04/04/11 |
Bad Block Management in NX2LP
Is Bad Block Management performed in NX2LP/NX2LP-Flex?
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Not yet rated
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04/04/11 |
EZ-USB Development Kit installation abort dialog box, "Error installing iKernel.exe"
While installing the Cypress EZ-USB, FX, FX2, SX2, and EZ-811 Dev Kit available as EZ-USB_devtools in "CY3681 FX2 DVK" on a Windows XP machine, the following error message: "Error installing iKernel.exe: (0xa00)" occurred. The dialog box has a title of "USB Control Panel" and the installation aborts when clicked "OK". What does this error message mean?
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Not yet rated
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04/04/11 |
Changing VID / PID without using Keil in AT2LP
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Not yet rated
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04/04/11 |
FX2 USB Interrupt Priority
Timer period is affected when USB traffic happens? Why is thi sproblem occuring since the TRM states that timer 1 interrupts have priority over USB interrupts?
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Not yet rated
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04/04/11 |
Crystal Specification of the EZ-USB AT2LP
Can the same crystal be used in an EZ-USB AT2LP (CY7C68300B) based device as the one used for an AT2 device?
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Not yet rated
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04/04/11 |
FX2 power consumption when using it as a standard microcontroller (not connected to USB)
In the FX2/FX2LP datasheet, Icc is specified when connected to USB FS and USB HS. What is Icc if the FX2/FX2LP is connected to neither? (e.g. just using the 8051 with a power supply)
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Not yet rated
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04/04/11 |
Can the External INT4 be Used With the GPIF/FIFO Auto- vectored Interrupts?
Can the external INT4 be used along with the GPIF/FIFO auto vectored interrupts? Where will the processor vector for INT4 if both are enabled?
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Not yet rated
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04/04/11 |
The Relationship Between the 8051 and USB Interrupts
What is the difference between 8051 and USB interrupts in an FX2LP Device?
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Not yet rated
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04/04/11 |
Alternatives to DASP# for Disk Activity Indication
What are the alternatives to DASP# for Disk Activity Indication?
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Not yet rated
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04/04/11 |
Crystal requirements for the CY7C68023A/CY7C68024A EZ-USB NX2LP.
What are the Crystal requirements for the CY7C68023A/CY7C68024A EZ-USB NX2LP?
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Not yet rated
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04/04/11 |
Device Descriptor Table Data
What is the file dscr.a51 used for?
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Not yet rated
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04/04/11 |
Compact Flash (CF) media change detection with the CY4611 board.
Compact Flash (CF) media change is not always detected with the CY4611 board.why?
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Not yet rated
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04/04/11 |
Purpose of the RESET#/OE# circuit controlled by Q1 on the FX2 Mass Storage Reference Design.
What is the purpose of the RESET#/OE# circuit controlled by Q1 on the FX2 mass storage reference design?
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Not yet rated
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04/04/11 |
Sending Byte Packets Out of GPIF at High Speed
I'm developing FX2 firmware that uses an EP2 1024 byte Interrupt mode endpoint. I'm trying to send 1024 byte packets out the GPIF at the highest possible speed after determining that the target FIFOs are not full. The GPIF waveform has write enables and mode bits in the CTL signals, so I can't go through IDLE except at packet boundaries without disrupting the target. I've tried AUTOOUT=1, and it seems the FX2 is sending multiple 1024 byte packets without going through IDLE. I need to go through IDLE every 1024 bytes to test the target FIFO. How?
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Not yet rated
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04/04/11 |
FIFO byte count registers
Explain the count value present in EPXFIFOBCH, EPXFIFOBCL registers.
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Not yet rated
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04/04/11 |
Where do I Find Complete Flowstate / UDMA Information For FX2
Page 15-87 of the Technical Resource Manual says, "For complete Flowstate / UDMA information, please contact the Cypress Semicondutor Applications Department." Where do I find this information about how to use the flowstate?
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Not yet rated
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04/04/11 |
Configuration of FX2/FX2LP to GPIF Mode
How do I configure the FX2 to go into GPIF Mode?
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Not yet rated
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04/04/11 |
Data Transfer between the Internal FIFOs and an External Memory Device in FX2/FX2LP
Can FX2/FX2LP transfer data between its internal FIFOs and an external memory device?
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Not yet rated
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04/04/11 |
Long Transfer Mode with CY7C68013 FX2
What steps do I need to take to get the long transfer mode to work with CY7C68013, or what steps do I need to take to get transfers to work without using the transaction counter?
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Not yet rated
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04/04/11 |
Synchronous/Asynchronous Mode From the SAS Bit in the FX2/FX2LP
How do you choose the synchronous/asynchronous mode from the SAS bit of the FX2/FX2LP?
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Not yet rated
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04/04/11 |
Application of T0/T1/T2 Pins in FX2
What is the typical application for signals T0/T1/T2 (pins 29-31 in the 128-pin package) in FX2?
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Not yet rated
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04/04/11 |
FX2LP REVCTL Settings for AUTOMODE Operation.
The FX2LP Technical Resource Manual section 9.3.4 mentions that the REVCTL bits DYN_OUT and ENH_PKT must be set to 1. But if these bits are set to 1, the FIFO cannot accept the OUT data. If these bits are set to 0, the FIFO cannot be reset well sometimes. Why should the REVCTL bits be set to 1? Is Figure 9-28 in the FX2 technical resource manual correct?
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Not yet rated
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04/04/11 |
Streaming Video in the 8051 (FX2/FX2LP)
What is the FX2's processor doing in the middle of continuous streaming video?
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Not yet rated
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04/04/11 |
Buffering Configuration to Guarantee Three Packets Per Uframe ISO Operation for the FX2LP.
What minimum buffering configuration is needed to guarantee three packets per micro frame isochronous operation on the FX2LP
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Not yet rated
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04/04/11 |