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Title
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Customer Rating
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Updated
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Buffering Interrupts.
The datasheet states that once the external master initiates a read request, all interrupts are buffered and the next interrupt from the SX2 is exclusively meant for the availability of the data from the read register request. When the external master has initiated a read request, and the SX2 triggers an interrupt ,interrupt status byte is seen instead of the read register request. Once the interrupt is cleared the next interrupt triggered has the value of the read request. So,when does the interrupts actually begin to get buffered ?
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Not yet rated
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06/10/11 |
Power supply decoupling required for HOTLink products
What special power supply decoupling is required for HOTLink products?
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Not yet rated
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06/10/11 |
Problems Writing Short Packets
I've already been able to do a bulk IN transfer using the FX processor as an external master (which will be eventually replaced by a DSP), but I still have the following problem: I'm trying to write a short byte array to EP6 (less than 512, which is the default). I'm using the register version of the PKTEND signal (e.g. writeregister(0x20, 0x04)), but it does not seem to commit the FIFO content to USB. How should this be done? I have successfully received data using the EZ-USB Control Panel writing 512 bytes to EP6 (from the perpheral), and doing a bulk read with length=512. Changing the bulk read length to anything else makes the communication fail.
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Not yet rated
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06/10/11 |
SX2 as a Universal Serial Bus Host.
Can the CY7C68001 be used with a MPC860 as a host in a USB network? If not, what is the alternative device for this application. If it can, is there a special configuration to set it up as the HOST or peripheral?
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Not yet rated
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06/10/11 |
Errors during UDMA data transfers in CY4611B
How does CY4611B handles CRC and parity errors during UDMA data transfers to ATA and ATAPI devices?
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Not yet rated
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06/10/11 |
Detecting ATA/ATAPI device on 40-pin ATA connector using CY4611B Firmware
In Cy4611B reference design how does the firmware detect if the attached device on 40-pin ATA Bus connector is ATA or ATAPI type?
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Not yet rated
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06/10/11 |
Relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode
What is the relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode?
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Not yet rated
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06/10/11 |
Framework files for FX1/FX2LP.
Where can I find the framework files of FX1/FX2LP?
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Not yet rated
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06/10/11 |
Error codes into string when using CyAPI.lib
How to convert error codes (CCyUSBEndPoint::NtStatus) into meaningful string when using CyAPI.lib?
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Not yet rated
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06/10/11 |
Avoiding “Found New Hardware Wizard” popup window in Windows
How to avoid “Found New Hardware Wizard” popup window in Windows when connecting the USB device?
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Not yet rated
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06/10/11 |
Enumerating SX2 in FULL Speed mode
How can I force the SX2 to enumerate in full speed mode only?
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Not yet rated
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06/10/11 |
Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX?
Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX?
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Not yet rated
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06/10/11 |
FX2LP is not enumerating when vend_ax.hex is downloaded into it. Why?
When I download vend_Ax firmware to FX2LP, it does not renumerate with the VID/PID that is specified in the dscr.a51 unlike the other code examples. Why?
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Not yet rated
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06/10/11 |
Reliable Enumeration of CY7C656xx Hub with Reset Consideration
What kind of situation CY7C656xx does not enumerate with the default descriptor?
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Not yet rated
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06/10/11 |
SX2 Crystal Oscillator Input
While using CY7C68001, if a 24MHz clock is already in the system, can it just be routed directly to the XTALIN pin, and leave the XTALOUT pin unconnected?
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Not yet rated
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06/10/11 |
Reset Signal High Duration for the CY7C68001 EZ-USB SX2
Does it matter how long the reset line is hold at high before going to reset?
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Not yet rated
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06/10/11 |
CY7C68001 EZ-USB SX2 INT# Pin Behavior for Multiple Interrupts.
The EZ-USB SX2 is capable of buffering multiple interrupts and INT# should be asserted if there is one or more pending interrupts. Must multiple interrupts be captured by an edge-triggered or level-triggered interrupt pin on the external master? For example, when there are two pending interrupts, reading the interrupt status byte clears the first interrupt. However, there is still one more pending interrupt, so the INT# line should be asserted again.
INT# ___/ \__
(1) (2)
INT# ______
(1) (2)
Which waveform is correct?
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Not yet rated
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06/10/11 |
Flushing the SX2 Read/Write FIFO
Should the SX2 FIFO be flushed before read/write?
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Not yet rated
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06/10/11 |
The way SX2 Clears the Status of the FLAGS and Other Interrupts.
How does SX2 clear the status of the FLAGS and other interrupts?
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Not yet rated
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06/10/11 |
Handling of USB bus reset by External master interfaced to SX2
How does the external master handle the case where SX2 receives a USB bus reset?
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Not yet rated
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06/10/11 |
External master and Data in SX2 FIFO
How does the external master determine if there's data in the SX2 FIFO to be read?
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06/10/11 |
SX2 Current Consumption
How much current does the SX2 consume in the unconfigured state (until enumeration is completed)?
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Not yet rated
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06/09/11 |
Connecting SX2 to both USB 1.1 and USB 2.0
Is it possible to connect the SX2 to USB 1.1 and 2.0 host controllers or only to USB 2.0 host controllers?
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Not yet rated
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06/09/11 |
Renumeration process in SX2 .
How is renumeration procedure possible if firmware cannot be uploaded to the SX2?
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Not yet rated
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06/09/11 |
Post-enumeration Initialization Steps -- SX2
What are the typical initialization steps the external processor needs to take after SX2 enumerates?
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Not yet rated
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06/09/11 |
Physical Interface and CPU Responsibilities for the SX2
What physical interface is presented to the external master or CPU from the EZ-USB SX2? What is the external master or CPU responsible for?
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06/09/11 |
Chip Select CS# Pin of SX2
What is the functionality of CS# of SX2 (CY7C68001)?
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Not yet rated
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06/09/11 |
Asynchronous FIFO Reads in the SX2
Is there an efficient way to learn how many bytes can be read from an OUT FIFO without checking the EmptyFlag after each byte read?
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06/09/11 |
Using SX2 as the clock source.
Can the SX2 be used to clock an external device? If so, what are the steps?
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Not yet rated
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06/09/11 |
SX2 Processor.
Does the SX2 have a processor (8051 ) like the FX2? If so, how is it different from the FX2?
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Not yet rated
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06/09/11 |
TCLK when TAP controller disable
To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. If tie high is the same, pull up, just not leave it float.
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Not yet rated
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06/09/11 |
Difference in version Standard, L and LL
What are the differences between the Standard, L version and LL version?
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06/09/11 |
Steps to get started with CY3655 Kit
What are quick steps to get started with CY3655 Kit?
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Not yet rated
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06/09/11 |
Effect on Programming because of 'black' ISSP cable instead of 'yellow' ISSP cable
The CY3655 Hardware User Guide document mentions a 'yellow' ISSP cable for programming purposes, but the CY3655 dev kit that I got has only a black ISSP cable. Could this cause issues while programming?
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Not yet rated
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06/09/11 |
Causes for Invalid Memory Reference(IMR) errors in PSoC Designer when debugging and not when my device is free-running
What are the causes for 'Invalid Memory Reference'(IMR) errors in PSoC Designer when debugging and not when my device is free-running?
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Not yet rated
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06/09/11 |
Message 'Could not connect to ICE'
When I try to run the drawusb project I get a "Could not connect to ICE" message. How do I resolve this?
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Not yet rated
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06/09/11 |
CY3655 kit example project for EnCore II
Why can't I find the example project, "Draw USB" for Encore II - CY7C63xxx in the Example Projects folder in PSoC Designer installation directory?
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(5/5) by 1
user
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06/09/11 |
MiniProg programmer - Pros and Cons related to enCoRe II devices
What are the pros and cons of using MiniProg for programming encoreII devices?
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Not yet rated
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06/09/11 |
C sample code for M8 parts
Do you have any M8 sample code written in C?
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Not yet rated
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06/09/11 |
Demo version vs. Full version of the BYTECRAFT C Compiler
What is the difference between the demo version and the full version of the BYTECRAFT C Compiler?
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Not yet rated
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06/08/11 |
Devices supported by BYTECRAFT C Compiler
Which devices are supported by BYTECRAFT C Compiler?
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06/08/11 |
Availability of the BYTECRAFT C Compiler
Is the BYTECRAFT C Compiler available?
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Not yet rated
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06/08/11 |
The ByteCraft C compiler doesn't correctly do bitwise operations on the port data registers.
Why doesn't the ByteCraft C compiler correctly do bitwise operations on the port data registers?
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Not yet rated
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06/08/11 |
Power measurements for low power modes of PSoC 3/5 on CY8CKIT-001
I want to test the low power mode current consumption on PSoC3/5. How should I measure it on CY8CKIT-001?
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(1/5) by 4
users
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06/07/11 |
Proximity sensing using CSD
How to configure a proximity sensor with CSD UM?
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Not yet rated
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06/03/11 |
MiniProg3 connections for bootloading over I2C
How should I connect the MiniProg3 to a DVK board, to bootload over I2C?
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Not yet rated
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06/01/11 |
Linux driver for CY7C65630 USB Hub
Does CY7C65630-56LFXA / USB Hubs have linux driver?
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Not yet rated
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05/31/11 |
Implementing SX2 design on FX2
The SX2 device is currently connected to a parallel EMIF on a DSP processor. We use the SX2 device to send a descriptor, handle the enumeration and then get out of the way while we transmit data. We used flags to determine when a buffer is empty to reload it with new data. Can this be done the same way in the FX2 device?
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Not yet rated
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05/31/11 |
ISR connected to Timer Interrupt is being executed multiple times.
The ISR connected to Timer interrupts seems to get executed multiple times. Why is it so and how to solve this problem?
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Not yet rated
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05/31/11 |
Streaming Throughput of an FX2LP Device
What are the factors on which the streaming throughput of an FX2LP Device depend upon?
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Not yet rated
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05/31/11 |