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Title
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Customer Rating
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Updated
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Instruction executed after PSoC 3/5 wakes from Sleep/Hibernate mode
What instruction will be executed first when PSoC 3/5 wakes up from sleep/hibernate mode?
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Not yet rated
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06/12/11 |
Skipping generation of APIs of a component in PSoC Creator
Is there a way so that I can stop generating APIs for the components for which I do not want to use them?
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Not yet rated
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06/12/11 |
"No Kits or Solutions Found" error message while opening PSoC Creator
In the start page of PSoC Creator I am getting "No Kits or Solutions Found". How to solve this?
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Not yet rated
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06/12/11 |
Available PSoC 3 pin packages
What are the available PSoC 3 pin packages?
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Not yet rated
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06/12/11 |
Selecting a PSoC 3 part number based on requirements in Cypress Website
How to select a specific PSoC 3 part number based on my requirements in Cypress Website?
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Not yet rated
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06/12/11 |
Difference between XRES and configurable XRES in PSoC 3/5
What is the difference between XRES and configurable XRES (P1[2]) in PSoC 3/5?
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Not yet rated
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06/12/11 |
USBFS Not Appearing as Bootloader I/O in PSoC Creator
My USBFS component does not appear as the Bootloader I/O component in the Systems tab of design wide resources in PSoC Creator. How to solve this?
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Not yet rated
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06/12/11 |
Inverting the display of characters on 16x2 character LCD in PSoC Creator design
How to Display inverse of characters (i.e. to toggle dots which are On to Off and visa-versa) on 16x2 character LCD interfaced with PSoc 3/5 using PSoC Creator?
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Not yet rated
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06/12/11 |
Format of .cyacd file relating to PSoC 3/5 bootloaders
What is the format of bootloadable file ( *.cyacd ) created by PSoC 3/5 Bootloaders?
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Not yet rated
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06/12/11 |
Avoiding regeneration of source files in PSoC Creator
I do not want project’s configuration and source files to update. Is there a way to avoid creator to regenerate the source file on build?
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Not yet rated
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06/12/11 |
Migrating project from CY8CKIT-001 to CY8CKIT-030 or CY8CKIT-050
How do we make example project designed to work on CY8CKIT-001 to work with CY8CKIT-030 or CY8CKIT-050?
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Not yet rated
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06/12/11 |
Number of DelSig ADCs available in a PSoC 3/5 project
In PSoC 3/5 devices how many DelSig ADCs can be placed on a single chip?
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Not yet rated
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06/12/11 |
Avoiding changes in the source file to get overwritten in PSoC Creator
Whenever I modify the code in component’s generated source file, it gets removed whenever project is built in PSoC Creator. How to make modification to retain after build?
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Not yet rated
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06/12/11 |
Selecting the inductor value for Boost Regulator section of PSoC 3/5
How to select the right value of Inductor for the Boost Regulator section of PSoC 3/5?
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Not yet rated
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06/12/11 |
Connecting multiple interrupt sources on the same port of PSoC 3/5
Why can't I connect multiple interrupts on the same port? i.e., If I connect an ISR to pin P0[3], I'm not able to connect another ISR to pin P0[4].
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Not yet rated
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06/11/11 |
FIFOs vs Dual-ports
When is a FIFO used instead of a dual port? How do I select between a FIFO and dual-port for my application?
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(3/5) by 1
user
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06/11/11 |
Aggregate bandwidth and throughput of synchronous dual-ports
- How do you calculate bandwidth with dual-ports?
- What is the throughput of a particular dual-port?
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Not yet rated
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06/11/11 |
Using multiple devices to create a wider data path for synchronous dual port SRAM's
How can multiple dual-port devices be combined to create a wider data path?
Can I width cascade multiple dual-ports?
How would I set up the dual-port for width expansion?
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Not yet rated
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06/11/11 |
Depth and width expansion affect on board-level timing
How does memory depth and width expansion affect board-level timing?
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(5/5) by 1
user
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06/11/11 |
CY7C08xxV Read Cycle Latency
- Why is there no FT/PL pin in some of the synchronous dual-ports?
- What is the latency associated with read operations?
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Not yet rated
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06/11/11 |
Battery backed solutions for CY7C08xxV dual-ports
Why is the standby current rating (Isb) on these 2Mb (CY7C0851V) and 4Mb (CY7C0852V) dual-ports so high compared to the 1Mb devices? I would expect the difference in Isb to be fairly linear, but it is, in fact, several orders of magnitude greater. (10 mA vs. 10-50uA).
The complication comes in looking for a battery backup switcher. I've found none of these power monitors can handle >150uA of standby current. Does Cypress have an battery backed solution available for these high-density dual-ports?
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Not yet rated
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06/11/11 |
Simultaneous access in synchronous dual-ports
- Can I write to the dual-port at the same time from both ports?
- What happens when I read and write to the same location at the same time?
- What happens if I read from the same location at the same time?
- If both ports are running off the same clock how may clock cycles after I write can I initiate a read from the same address?
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(4/5) by 1
user
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06/11/11 |
Read-Back of Internal Address Counters for synchronous dual port SRAM's
- How can one see the current state of the internal counter?
- Is there a way to check the state the burst counter?
- Is address readback different for the CY7C08x1V / CY7C08x2V devices?
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Not yet rated
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06/11/11 |
Unused OE# and CE1 Pins
If I am not going to use these pins, what should I do with them?
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Not yet rated
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06/11/11 |
VSS vs. VSSQ for synchronous dual port SRAM's
What is the difference between VSSQ versus VSS in the datasheet?
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Not yet rated
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06/11/11 |
Burst Counter Operation and chip disabled for synchronous dual port SRAM's
If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock?
An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc. Note that output enable and counter enable will always be active. Could you confirm this for me?
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(5/5) by 1
user
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06/11/11 |
Read and Write with Single Internal Counter for Synchronous Dual port SRAM's
What happens if we write on one clock cycle with ADS#, CE# and CNTEN# all low (i.e. load the address counter) and then, on the next cycle we read without ADS# but with CNTEN# (i.e. increment the counter). Will the address we read from be one higher than the one we loaded in the first cycle?
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Not yet rated
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06/11/11 |
Timing relationship of OE# to the dual-port
What is the timing relationship between OE# and CE# in synchronous Dual Ports? - How is the output enable signal connected to the clocks?
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Not yet rated
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06/11/11 |
Internal Power-On Reset (POR) Circuitry in Synchronous Dual-Ports
Do synchronous dual-ports have internal power on reset circuitry?
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Not yet rated
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06/11/11 |
CE not present in some Dual port SRAM's E.g CY7C0853V
- How do I enable and disable this dual-port since there are no Chip Enable (CE#) pins?
- If I have R/W# tied low on one side (always writing), how can I stop it when I need to?
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Not yet rated
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06/11/11 |
Data hold time
Data that is read out of a synchronous dual-port holds valid for a minimum period of "tDC". What is the maximum value?
How long will the data read out (Qn) be available on the data lines after the clock edge?
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Not yet rated
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06/11/11 |
Aligning byte enables for synchronous dual port
- If I connected a 32-bit processor to a 36-bit wide dual-port, how can I align the byte enables?
- Can I use the byte enables of the 18-bit wide dual-port if my system is only 16 bits?
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Not yet rated
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06/11/11 |
Migration from FLEX 72 to FLEX 72-E
- How to migrate from FLEx72 Migration to FLEx72-E ?
- What do the notes on page 2 of the datasheet mean?
- If I do not wish to use these features, what should I do with the pins?
- What do the pins labeled with a note do in the FLEx72-E?
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Not yet rated
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06/11/11 |
Partial access to Dual Port mailbox
Does writing or read only to the upper/lower byte (using LB# and UB#) of the mailbox trigger or clear the interrupt flag?
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Not yet rated
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06/11/11 |
Data valid period during two consecutive read cycles with the same address
During a flow-through read cycle, your datasheets specify that tCD1 after the rising edge of the read CLK, data is ready to be read. They also specify that the data will remain valid for tDC. My question is what would happen if you perform two flow-through read cycles with the same address consecutively? The datasheet shows a data valid period followed by unknown data followed by the data valid period for the following read. Does this apply to this case? Or will the same valid data from the first read remain on the data lines until the end of the second read cycle?
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Not yet rated
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06/11/11 |
Burst Counter Wrap-Around
- What happens when I use the burst counter and reach the very last memory location?
- Does the internal counter return to 0 when I reach the end of the memory array?
- If the burst counter wraps around to 0, will I be able to continuously read the data on every clock cycle or do I have to pause my reading operations?
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Not yet rated
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06/11/11 |
Timing and clock skew in synchronous Dual port during simultaneous read and write at same location
What does it mean to violate tCCS when one port is writing and the other reading from the same location?
How does the timing differ depending on whether it is the read or the write that happens slightly before the other?
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Not yet rated
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06/11/11 |
Bus Matching in CY7C09569V/CY7C09579V Dual-ports
How do I set up the bus-matching features on my dual-port?
How can I change the bus matching set-up after initial power-up?
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Not yet rated
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06/11/11 |
FullFlex - Variable Impedance Matching/Variable Impedance Sensing in Fullflex dual ports
What is Variable Impedance matching (VIM), Variable impedance Sensing (VIS)? How does it work, what are its effects and what are resistor tolerances?
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Not yet rated
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06/11/11 |
FullFlex - Echo clocks and their timing benefits
Explain Echo clocks for FullFlex Dual ports SRAM's? What are their timing benefits?
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Not yet rated
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06/11/11 |
Configuring pipelined vs. flow-through mode after power up
Can the Flowthrough/Pipeline mode be reconfigured after power-up for some Full flex dual port SRAM's?
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Not yet rated
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06/11/11 |
FullFlex - Power sequencing for the Fullflex
How is Power Sequencing done for the Fullflex Dual Ports?
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Not yet rated
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06/10/11 |
CY7C0852V BSDL and JTAG
CY7C0852V BSDL and JTAG Questions: - What is wrong with the Pause-DR state? - How do you prevent going into the Pause-DR state? - What happens during JTAG testing when I enter Pause DR? - What happens to the CY7C0852V JTAG Chain in PAUSE-DR State?
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Not yet rated
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06/10/11 |
Stand-by Power Consumption of the CY7C0853V
What is the ISB (stand-by current) value for the CY7C0853V?
How can I save power on the 9M dual-port?
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Not yet rated
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06/10/11 |
Programming Failure using ICE Cube
I am trying to program my enCoRe II device in system through a USB cable. I am using the ICE Cube, yellow ISSP cable and 5-pin to USB adapter. I get an error message on my PSoC Programmer user window that says, Programming succeeded, verify failed; sometimes it fails to Acquire device. How can I resolve this?
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Not yet rated
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06/10/11 |
ESD Protection of USB 2.0 Device Inputs
ESD protection required of modern testing methods.
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Not yet rated
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06/10/11 |
INT Line Behavior
What happens if an interrupt from any other source occurs after the read register command has been issued and before the data is available on FD [7:0]?
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Not yet rated
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06/10/11 |
Typical System Transfer Rate for an SX2 Device
Can the SX2 give a system throughput of 20-30MB/s in bulk mode? If so, how should the device be configured?
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Not yet rated
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06/10/11 |
CY7C68001-Ready Signal
Would it be better to check the rising edge for Ready rather then doing a level sensitive check?
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Not yet rated
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06/10/11 |
SX2 Endpoint Register Default Values
After enumeration, do all the registers in SX2 have the default values shown in the SX2 Register Summary of the datasheet?
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Not yet rated
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06/10/11 |