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Title
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Customer Rating
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Updated
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Using /FF as a Half Full flag in depth cascaded FIFO's
If cascading two FIFO's in depth, can the full flag (/FF) of the first FIFO be used as the half full flag for both FIFO's?
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Not yet rated
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06/13/11 |
Replacing asynchronous FIFO's with synchronous FIFO's
- What design considerations are there when converting from an asynchronous FIFO to a synchronous one?
- What is different about designing with synchronous FIFOs?
- Can you operate a synchronous FIFO as an asynchronous one?
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Not yet rated
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06/13/11 |
Compiler for CY3650
Does a .rom file produced by a compiler work correctly on the CY3650 (or CY3651)?
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Not yet rated
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06/13/11 |
Requirement of Pull-up resistors on SCL and SDA lines when unsed
Is it required to connect pull-up and pull-down resistor on SCL and SDA lines when a device is not connected?
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Not yet rated
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06/13/11 |
Using GPIF pins ( RDY / CTL pins) for GPIO functionality in FX1 / FX2 / FX2LP
Can the GPIF RDYx and CTLx pins be used as generic input and output ports controlled directly by the 8051 when using the part in GPIF mode?? Specifically, can I use the GPIFREADYSTAT registers to sample the states of the RDYx pins, and the GPIFIDLECTL register to control the states of the CTLx output pins?
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Not yet rated
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06/13/11 |
CY3650 Development Kit Contents
What is included in the CY3650 Development Kit?
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Not yet rated
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06/13/11 |
Maximum Throughput Using FX2 (CY7C68013) GPIF Interface
What is the maximum sustainable transfer rate the FX2LP can obtain in GPIF transfer mode?
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Not yet rated
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06/13/11 |
Using RDY0 / RDY1 lines as GPIO in FX1/FX2/FX2LP
Can the GPIF's RDY0 pin can be used as a normal GPIO?
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Not yet rated
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06/13/11 |
Programming CY7C630xx/631xx using CY3650
Can the CY7C630xx/631xx parts be programmed with the CY3650?
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Not yet rated
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06/13/11 |
GPIFTC [B3:B0] Chip Revision - CY7C68013
In which chip revision was the GPIF transaction counter updated from 16 bits to the new 32-bit GPIFTC[B3:B0]?
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Not yet rated
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06/13/11 |
GPIO pins supported by CY7C68320/21.
How many GPIO pins does the CY7C68320/21 support?
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Not yet rated
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06/13/11 |
CY7C68300 / CY7C68300A - EZ-USB AT2 Must be Powered Before Attached Drive
Should CY7C68300 / CY7C68300A - EZ-USB AT2 be Powered Before Attached Drive?
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Not yet rated
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06/13/11 |
Suspend current specifications on the CY7C65640
Does the suspend current specifications on the CY7C65640 (100uA) include the current through the D+ resistor? What is the current flowing thru the internal D+ resistor during suspend?
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Not yet rated
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06/13/11 |
Unable to download the firmware (the .rom file) onto CY3650
I can't download the my firmware (the .rom file) onto my CY3650. When I download the file "test.rom", Why does the PC pop up a message saying "cmdDnldDnld_Click: DownLoad of test.rom ended before all valid characters were loaded into Program RAM. Stopped at Program RAM Address1"?
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Not yet rated
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06/13/11 |
CY3650 Setup
What are the step-by-step instructions to run firmware on CY3650?
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Not yet rated
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06/13/11 |
Setting up CY3650 CY3651 or CY3652
How do I set up the CY3650 CY3651 or CY3652?
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Not yet rated
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06/13/11 |
CYDB software for CY3650 (or CY3651, CY3652)
Can I run the CY3650 (or CY3651, CY3652) on the new CYDB software?
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Not yet rated
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06/13/11 |
State of TetraHub PWR# pins
What is the state of the PWR# pins when the hub is in a disconnected state from the host (BUSPOWER pin low) and the hub being a self powered device, is still in a powered state? Are these output pins still driven low or are they floating?
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Not yet rated
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06/13/11 |
CY7C68300 / CY7C68300A - CH8Ck Test Software from PIMC Reports Failures with the EZ-USB AT2
What are the invalid host behaviors when running Ch8Ck software?
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Not yet rated
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06/13/11 |
CY7C68300 / CY7C68300A -- Maximum Capacity of Hard Drive that the EZ-USB AT2 can Support
What is the maximum capacity of harddrive that the EZ-USB AT2 can handle?
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Not yet rated
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06/13/11 |
I just purchased a CY3652C Development kit and it fails the self-test program. The Device Manager shows UNKNOWN device.
I just purchased a CY3652C Development kit and it fails the self-test program. The Device Manager shows UNKNOWN device.
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Not yet rated
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06/13/11 |
Device manager sees attached device as 'Unknown Device'
When I run my firmware on the CY3650, under the Device Manager why does the host see my device as an 'Unknown Device'?
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Not yet rated
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06/13/11 |
Driver for the CY3650 DVK
When USB cable is plugged into the CY3650 board, the host sees it as an "Unknown Device". USB "selftest" is not seen. What is the driver for the CY3650? How to know if the development board is functioning correctly?
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Not yet rated
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06/13/11 |
Byte 7 of the EEPROM for a 0xD2 load.
How is byte 7 of the EEPROM interpreted? What is the purpose of the Enable Overcurrent timer and Disable Overcurrent Timer? What is the difference between these two parameters and how are they used?
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Not yet rated
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06/13/11 |
Is the TetraHub device USB compliant?
Is the TetraHub device USB compliant?
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Not yet rated
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06/13/11 |
Can the TetraHub interface with a small (1K/2K) EEPROM?
The reference design CY4602 of TetraHub USB Hub uses a 4K EEPROM. Can the TetraHub interface with a smaller (1K/2K) EEPROM?
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Not yet rated
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06/13/11 |
Are USB Hub drivers standard so that the user need not write a specific USB Hub class driver?
Are USB Hub drivers standard so that the user need not write a specific USB Hub class driver? The OS is Windows 2000 and XP.
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Not yet rated
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06/13/11 |
Buffer per TT?
While running the WHQL test on my TetraHub Device, the test asks for the buffer size per TT. What should I enter?
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Not yet rated
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06/13/11 |
TetraHub WHQL Certification
Is the TetraHub WHQL Certified?
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Not yet rated
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06/13/11 |
External Clock in PSoC Designer 5.0 SP5 does not work.
When System clock is selected as P1[4] in PD5.0 SP5, PSoC does not work. What is the problem and how do I make this working?
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(4.5/5) by 2
users
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06/13/11 |
Minimum PWM frequency in System level design
What minimum PWM frequency can be configured in System level design?
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Not yet rated
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06/13/11 |
Manually uninstalling PSoC Programmer / any other programs Cypress Software
How do I manually uninstall Cypress Software tools?
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(3.5/5) by 2
users
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06/13/11 |
What is the Best Way to Debug GPIF Applications?
What is the best way to debug my GPIF application?
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Not yet rated
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06/13/11 |
1-Wire Communication - Pull Up Resistor
Is an external pull up resistor required in 1-wire communication?
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Not yet rated
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06/13/11 |
CSD Parasitic Capacitance Calculator
How can I find the Parasitic Capacitance of my sensor from the raw counts? I am using CY8C21x34.
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Not yet rated
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06/13/11 |
Operating EZI2C in PSoC at lower than 50KHz frequency
I want to operate PSoC EZI2C as a slave in I2C communication. The I2C master clock frequency is 40KHz, but in designer the options available for CLK are 50KHz, 100KHz and 400KHz. Can PSoC respond to 40KHz ?
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Not yet rated
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06/13/11 |
SLRD/SLWR Pins During GPIF Mode of FX2LP
During GPIF burst transaction, is the GPIF in control of the SLWR, SLOE signals internally? Do I need to tie the appropriate CTLx output signals to these signals?
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Not yet rated
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06/13/11 |
EZ-USB FX2 GPIF Reference Materials
Are there any reference materials for the usage of EZ-USB FX2LP (CY7C68013A) GPIF engine?
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Not yet rated
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06/13/11 |
Current Status of the READYx Pins for the CY7C68013
Is it possible to read the current pin status of the GPIF ready lines through firmware?
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Not yet rated
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06/13/11 |
Restrictions/Limitations on using FX2LP IFCLK
Are there any concerns/restrictions/limitations on using IFCLK?
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Not yet rated
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06/12/11 |
WinCE Version For CyUSB.sys
Does Cypress provide a version of CyUSB.sys that is compatible with the WinCE OS?
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Not yet rated
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06/12/11 |
I2C Clock Stretching in FX2LP
Does the I2C controller of FX2LP support clock stretching?
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Not yet rated
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06/12/11 |
Can't Acquire Device - Error while Programming PSoC1
How do I correct the error message "Can't acquire device?"
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Not yet rated
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06/12/11 |
Enable MAC in Compiler Does Not Work
I cannot get the enable MAC to work.
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Not yet rated
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06/12/11 |
Build error - LMM info: 'Interrupt RAM' uses too many bytes
When I try to compile my project in PSoC Designer, I get the message:
Build error. LMM info: 'Interrupt RAM' uses 39 bytes in page 0.
and my project does not compile.
What do I need to do to make this work correctly?
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Not yet rated
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06/12/11 |
Accidental Modification of I/O Pins in PSoC1
I am unable to modify the state of a PSoC pin using instructions like PRTxDR |= 0x01, PRTxDR &= ~0x01. What am I doing wrong?
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Not yet rated
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06/12/11 |
DAC8 as Reference to a PGA
I am using the output of a DAC8 as reference to a PGA, but it does not work. What could be the reason?
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(4/5) by 1
user
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06/12/11 |
Difference between Factory Programmable and Field Programmable devices
What is the difference between Factory Programmable and Field Programmable devices?
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Not yet rated
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06/12/11 |
Change the "Select" type for pins in PSoC Designer firmware
How can I switch between "StdCPU" to "Global In" or "Global Out" bus within firmware?
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Not yet rated
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06/12/11 |
Drive strength differences between GPIO and SIO pins in PSoC 3/5
What are the differences in drive strength between GPIO and SIO pins in PSoC 3/5?
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Not yet rated
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06/12/11 |