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Title
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Customer Rating
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Updated
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Renumeration in firmware for FX1/FX2LP
How can I do renumeration in firmware?
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Not yet rated
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06/18/11 |
Ways of configuration of Endpoints 2,4,6 and 8 in FX1/FX2LP
What are the ways in which endpoints 2,4,6 and 8 be buffered?
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Not yet rated
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06/18/11 |
Read / Write control signals on unidirectional FIFOs
Why is there a read/write control signal (R/W#) on each port for a unidirectional FIFO?
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Not yet rated
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06/18/11 |
Writing at the Full Boundary
- What happens if FIFO is continuously write into when Full Flag is asserted?
- My system is set up to continuously write until the FIFO is full. Once it is full, I begin to read out the data. However, it seems like I lose some of the data being written into the FIFO when I do so. RCLK and WCLK are the same. What is wrong?
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Not yet rated
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06/17/11 |
PIO and UDMA Settings of the ISD-300A1
How to distinguish between the PIO and the UDMA settings?
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Not yet rated
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06/17/11 |
Usage of the Output Enable (OE) Signal in Synchronous FIFOs
1. If OE is high, what happens to the data bus?
2. If there is a valid read operation, but OE is high, will the next read operation be the same word or the following word in the FIFO?
3. If OE is high during reset, will the data bus remain in a high-Z state?
4. Is it okay to connect the OE pin to ground?
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Not yet rated
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06/17/11 |
High speed monitor
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Not yet rated
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06/17/11 |
Synchronous FIFO architecture
What is the architecture of the Synchronous FIFOs? Is the memory managed by pointers or shifting registers? If the fullness of the FIFO is managed well, is it possible to endlessly read and write?
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Not yet rated
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06/17/11 |
Usage of different speed grades in synchronous FIFOs
- Can I replace a -35 device with with a -25 device?
- If the two ports of my FIFO are running at different rates, how do I pick a speed grade for my system?
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Not yet rated
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06/17/11 |
Driving REN1 and REN2 together for some families of synchronous FIFO's
- Can I drive /REN1 and /REN2 with the same signal?
- Can I tie Read Enable 1 and Read Enable 2 together?
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Not yet rated
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06/17/11 |
Retransmit feature of synchronous FIFO's
- What happens to the data lines when RT is pulsed and during the tRTR time?
- Can a selected block of data be retransmitted?
- What considerations are there for using the retransmit operation?
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Not yet rated
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06/17/11 |
Delay buffers using synchronous FIFOs
How can I make a delay buffer that always has x number of words in the buffer?
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Not yet rated
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06/17/11 |
Synchronous FIFO Clocks
- Are there any requirements for clock duty cycles?
- Do the clocks have to have 50 percent duty cycles?
- What are the requirements for the clock driving sync FIFOs?
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Not yet rated
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06/17/11 |
Output State for the FIFOs
- Can I make the data outputs (Q0 - Q8) to be normally high?
- What is the status of the data outputs after reset?
- What happens to the data outputs when /OE is asserted?
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Not yet rated
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06/17/11 |
Driving 3.3V I/Os on a 5V device
- Can I drive 3.3V I/Os into a 5V part?
- What are the minimum input levels for 5V devices?
- Will my 3.3V processor be strong enough to connect to a 5V device?
- Will a -1V undershoot on the inputs cause problems?
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Not yet rated
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06/17/11 |
Usage of XI#, XO#, and FL#/RT signals
- What should pin XOn, /XO, RXOn, /RXO, RXIn, /RXI, WXOn, /WXO, WXIn, /WXI, FLn, /FL be tied to if I am not cascading?
- What should these pins be tied to if I am width cascading?
- What should these pins be tied to if I am depth cascading?
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Not yet rated
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06/17/11 |
Maximum number of cascaded FIFOs
How many FIFOs can I cascade in depth and by width? What are the considerations?
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Not yet rated
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06/17/11 |
Using a FIFO as a transparent device
- Can the FIFO be used transparently?
- Can data written into the FIFO be read straight out?
- Can one tie WCLK and RCLK together?
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Not yet rated
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06/17/11 |
CY3267, CY3268 OCD and EEPROM issues
The below two issues are encountered with the CY3267/CY3268:
1.While trying to connect to the debugger , the error message “Attached pod (00bf0022) is not compatible with the selected PSoC” is thrown.
2.While writing to the EEPROM using the E2PROM module, the API 'E2PROM_bE2Write' returns a value of ‘-1’ indicating write failure.
Why is this so and what is the solution?
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Not yet rated
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06/17/11 |
CY3269N - Low Battery Functionality
What should I do if the HBLED on CY3269N flickers and stays off even though the board seems to be powered on (D3 – Red LED is ON)?
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Not yet rated
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06/17/11 |
CY3267 PowerPSoC Lighting Evaluation Kit - GUI Known Issues and Workarounds
CY3267 - Intelligent Lighting Control 64-bit OS Support, Unhandled Exception and Communication Break
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Not yet rated
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06/17/11 |
Asserting the PKTEND strobe
When operating in slave FIFO mode, can the external master assert the packet-end pin on the same rising edge of IFCLK when the last write into the FIFO occurs?
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Not yet rated
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06/17/11 |
Purpose of the SLCS# pin of the CY7C68013 (FX2)?
What is the purpose of the SLCS pin. Do I have to use this pin for interfacing/accessing the endpoint FIFOs?
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Not yet rated
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06/17/11 |
Timing specification between SLOE and SLRD in EZ-USB FX2
There are no timing restrictions between SLRD and SLOE specified in the FX2 datasheet. Can you please clarify what is the timing requirement between SLOE and SLRD for FIFO read in synchronous and asynchronous mode?
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Not yet rated
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06/17/11 |
Example on Slave FIFO for FX2
Do you have any examples of the Slave FIFO Interface on the FX2?
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Not yet rated
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06/17/11 |
Driving IFCLK on the CY7C68013
Does IFCLK need to be driven continuously, or only when the SLxx pin is set LOW?
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Not yet rated
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06/17/11 |
Handling Odd Count Packet Sizes Between an FX2-SX2 16-bit WORDWIDE Interface
When an odd number of bytes (eg. 45 bytes) are sent from FX2's EP2OUT to SX2's EP6IN, the SX2 receives it in word form and it is considered 23 words, since we are using a 16-bit WORDWIDE interface across the two chips.
When the words are converted back to bytes later, the SX2 will multiply it by 2 and becomes 46 bytes in the endpoint FIFO instead of the original 45 bytes originally sent. What should be done to ensure that the byte count in SX2 is 45 bytes in this case?
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Not yet rated
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06/17/11 |
Setting Polarity for FIFO Programmable-level Flag (PF) on the FX2 (FX2 - BHA)
How do I set polarity for FIFO programmable-level flag (PF)?
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Not yet rated
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06/17/11 |
Physical Interconnect Between External Master and FX2 Slave FIFO Interface
I would like an example physical interconnect between our external master and the FX2's Slave FIFO Interface. Where can I find one?
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Not yet rated
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06/17/11 |
Do I Need to Monitor the FIFO Flag Status When Using the FX2 as a Slave for Payload Data?
If I am primarily using FX2 in Slave FIFO mode as a conduit for payload data, do I need to monitor the status of FIFO flags?
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Not yet rated
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06/17/11 |
Different Register Values EPxFIFOFLGS vs. EPxxFIFOFLAGS (FX2)
What is the difference (if any) between the value of the Flag bits in the EPxFIFOFLGS, EPxxFIFOFLGS and EP2468STAT registers?
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Not yet rated
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06/17/11 |
Slave FIFO Mode Synchronous Burst Read/Write with the CY7C68013 (FX2)
Does the FX2 device support synchronous burst read/write in slave FIFO mode? In the FX2 Technical Reference Manual, I am unable to find an I/O waveform of synchronous burst read/write with SLRD/SLWR asserted for the entire burst duration.
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Not yet rated
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06/17/11 |
Slave FIFO Address Lines for the CY7C68013 (FX2)
Figures 9-11 and 12 in the Technical Reference Manual present a small state machine on how to perform FIFO writes in asynchronous mode. Is it necessary to pass all the states in the state machine described in this section? Can I set FIFOADDR lines before one clock, perform a write cycle on the next clock, and subsequently change FIDOADDR lines in order to perform a write to a different endpoint?
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Not yet rated
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06/17/11 |
FX2 HID device unable to respond to the Get_Report_Descriptor request
I am using the bulkloop example as a basis to design a HID device using the FX2. I have defined the HID descriptor correctly as stated in the HID spec but the FX2 fails to respond to the GET_HID_DESCRIPTOR request. Do you have an example that shows how to design a HID device using FX2?
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(1/5) by 1
user
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06/17/11 |
EZ-USB FX2 Performance and Memory Size
We want to use the EZ-USB FX2 (CY7C68013-56PVC) chip on our demo board. We intend to use the chip's slave FIFO I/F in synchronous mode. The interface is coupled to an FPGA for further processing. This FPGA will then be the master for the slave FIFOs.
1) How can the local transfer rate of 96 MB/s be achieved? Is it necessary to use the chip in the GPIF mode? With 48 MHz and a 16 bit data bus this would require that Ican transfer a data word (16 bit) per IFCLK cycle. But that is not possible according to Chapter 9 of the Technical Reference Manual. When I look at your example waveforms it seems at least two cycles, or actually three with "State 4", are required. How does this fit into the performance of 96 MB/s? Is it possible to transfer 16-bit data words in one cycle? Or do I need to use one cycle for reading the data, and one cycle to check the FIFO flag and update the FIFO pointer? In this case I only have a performance of 48 MB/s.
2) The setup times for read and write are almost one clock cycle when working with the 48 MHz internal IFCLK. Do I need an additional cycle to set up SLWR or SLRD? Would this further decrease the performance.?I can't see how an inverted clock would help - it makes things even worse. Unless of course I may keep the SLWR or SLRD active during e.g. a packet read where I transfer a data word on each clock cycle!?If I use an external IFCLK, according to the data sheet I get better set-up times, but then I have stronger requirements for the hold time.
3) What is the exact amount of memory inside the chip for the Endpoints EP2, EP4, EP6, and EP8? Are endpoint buffers and endpoint FIFO two separate memory areas or one? Is there a physical memory space for both the FX2 memory space (containing endpoint buffers) and additional 4KB for the FIFOs?
The way I see it, two possbilities exist: a) FX2 memory has space for 3KB (e.g 6x buffers of 512 bytes each); or b) The FIFOs have a space of 4KB. According to your data sheet, an area of 2x 512 bytes in the FX2 memory space is reserved, which explains that a buffer for EP4 and EP8 only can be 512 bytes. The FIFO space (if it is extra space?) has a total of 4KB with no reserved areas, right?
4) When exactly are full and empty flags asserted? On a byte, 16-bit word, USB packet, or user defined packet size level? I need this exact information for both reads or writes to a slave FIFO endpoint. The technical reference manual fails to offer
precise information on that.
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Not yet rated
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06/17/11 |
Speed Up Slave FIFO Transfer (FX2)
Can I speed up a Slave FIFO transfer by asserting SLWR for consecutive IFCLK cycles, assuming the the programmable flag is continuously monitored?
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Not yet rated
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06/17/11 |
Achieving a Local Transfer Rate of 96MB/s in FX2
How can the local transfer rate of 96 MB/s be achieved?
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Not yet rated
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06/17/11 |
Slave FIFO/GPIF Usage With FX2
Can I use the CY7C68013's Slave FIFO and GPIF interface at the same time?
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Not yet rated
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06/17/11 |
External Logic Read of the CY7C68013
When using the C7C68013, is there a limit on the number of words/bytes the external logic can read from the FIFO at one time? For instance, when the empty flag is not asserted and the external logic has read 512 bytes from a quad buffered FIFO, does the external device need to stop and check the empty flag before beginning to start reading again?
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Not yet rated
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06/17/11 |
Read IOCTL failed Message in the Control Panel While Strobing SLWR Continuously - CY7C68013
When requesting a Bulk IN transfer using the EZ-USB Control Panel while strobing SLWR continuously, the response is a "Read IOCTL failed" message. Can some other part of the hardware be damaged?
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Not yet rated
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06/17/11 |
BL51: ERROR 107 (ADDRESS SPACE OVERFLOW)
I receive the following linker error when I compile and link my program:
*** ERROR L107: ADDRESS SPACE OVERFLOW
SPACE: DATA
SEGMENT: _DATA_GROUP_
LENGTH: 0014H
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Not yet rated
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06/17/11 |
About REVCTL
What is the REVCTL operation in EZ-USB FX2 and its use in general in the slave FIFO application, when the endpoint is set to auto mode?
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Not yet rated
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06/17/11 |
I2S interface support for FX2LP devices
Does FX2LP devices support I2S interface?
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Not yet rated
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06/17/11 |
AT2LP support for Selective suspend and Remote Wakeup
Does the AT2LP support Selective suspend and Remote Wakeup?
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Not yet rated
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06/17/11 |
FX2LP I2C operating speed is lesser than the expected value
In FX2LP’s I2C interface, when we select 400 kHz, we only get ~300 kHz bus speed. Similarly when we select 100 kHz, we get ~85 kHz. What is the reason?
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(2/5) by 1
user
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06/17/11 |
Using MLC (Multiple-Level Cell) Flash Nand with NX2LP
Can we use MLC (Multiple-Level Cell) Flash Nand with NX2LP?
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(1/5) by 1
user
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06/17/11 |
CY7C68300 / CY7C68300A - 24MHz crystal of the AT2
The manual states that a 24MHz crystal is recommended, but can another type of crystal be used?
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Not yet rated
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06/17/11 |
CY7C68300 / CY7C68300A - Driver Support for the EZ-USB AT2
Which Cypress driver supports the EZ-USB AT2?
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(5/5) by 1
user
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06/17/11 |
CY7C68300 / CY7C68300A - Alternate EEPROM for EZ-USB AT2
Can I use a different EEPROM with the EZ-USB AT2?
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Not yet rated
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06/17/11 |
Crystal requirements for the CY7C68300B/CY7C68301B/CY7C68320/CY7C68321 EZ-USB AT2LP parts
What are the crystal requirements for the CY7C68300B/CY7C68301B/CY7C68320/CY7C68321 EZ-USB AT2LP parts?
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Not yet rated
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06/17/11 |