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Title
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Customer Rating
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Updated
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AN21xx EZ-USB development board PLD source file
I am using the AN21xx EZ-USB family of chips. Is the source file for the PLD available?
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Not yet rated
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11/16/11 |
Wiring AVCC and AGND in EZ-USB FX2
How do you recommend the analog signal lines, AVCC and AGND be wired in the EZ-USB FX2?
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Not yet rated
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11/16/11 |
Broker Letter.
Will Cypress provide support on Cypress part purchased from unauthorised channel.
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Not yet rated
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11/15/11 |
Dietemp user module in PSoC Designer 5.1 Beta2
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Not yet rated
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11/15/11 |
What is the difference between the SL11 and the SL11T?
What is the difference between the SL11 and the SL11T?
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Not yet rated
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11/15/11 |
Keyboard Example for EZ-USB family Controller
Do you have any examples for a USB Keyboard with an EZ-USB family controller?
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Not yet rated
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11/15/11 |
Spice/VHDL/Verilog model for EZ-USB family of chips
Are there any spice/VHDL/Verilog model available for EZ-USB family (FX, AT2, SX2, TX2, NX2 series) of chips?
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(3/5) by 1
user
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11/15/11 |
Interrupt endpoint handling for EZ-USB
What special code changes does my application and firmware require for interrupt endpoint?
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(1/5) by 1
user
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11/15/11 |
How to interface the EZ-USB AN21xx to an MCU (generic 8051)?
I would like to interface the EZ-USB AN21xx to an MCU (generic 8051). How can I do this?
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Not yet rated
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11/15/11 |
AN2131 Crystal Jitter
Is the crystal the primary source of jitter?
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Not yet rated
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11/15/11 |
How do I input an external clock to AN21xx (as opposed to the crystal)?
How do I input an external clock to AN21xx (as opposed to the crystal)?
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Not yet rated
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11/15/11 |
How do I make your EZ-USB development board work in Windows 95?
How do I make your EZ-USB development board work in Windows 95?
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Not yet rated
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11/15/11 |
Generate frameworks (fw.c)
How to generate a frameworks (fw.c) based project?
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Not yet rated
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11/15/11 |
What type of serial eeprom compatible boot loader is supported for AN21xx family chip
What type of serial eeprom compatible boot loader is supported for AN21xx EZ-USB family chip?
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Not yet rated
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11/15/11 |
EZ-USB Control Panel User Guide for AN2131-DK001
Do you have any EZ-USB Control Panel User Guide for AN2131-DK001?
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Not yet rated
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11/15/11 |
Does the clock multiplier (12MHz --> 48/24MHz) inside the EZ-USB (AN21xx) family uses an analog or a digital PLL?
Does the clock multiplier (12MHz --> 48/24MHz) inside the EZ-USB (AN21xx) family uses an analog or a digital PLL?
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Not yet rated
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11/15/11 |
Interface EZ-USB AN21xx to 5V TTL Logic
Can you interface the AN21xx EZ-USB to 5V TTL Logic?
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Not yet rated
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11/15/11 |
Change the values in configuration descriptor for the Self-powered hub for CY7C66113
How does the hub handle the GetStatus requests by changing the values in configuration descriptor (bmAttributes=self-powered and MaxPower=0)?
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Not yet rated
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11/15/11 |
CY8PLC10 temporarily stalls I2C when transmitting
I am communicating properly with CY8CPLC10 over I2C, and sending PLC message over the powerline. During transmission, I am polling the status register (0x69) to see when it is complete. During this time, the CY8CPLC10 does not complete the I2C Stop protocol - it holds the SCL line low until the transmission is completed. Is this correct operation?
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Not yet rated
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11/14/11 |
Export data option doesn't work in CapSense Express Tuner
Export data option doesn't work in CapSense Express Tuner window of PSoC Designer 5.0 SP6
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Not yet rated
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11/09/11 |
CapSense sensor scan time mentioned in CSD2X user module datasheet does not match with measurement from hardware
Why does the CapSense sensor scan time mentioned in CSD2X user module datasheet does not match with measurement from hardware?
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Not yet rated
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11/03/11 |
Unable to see Program button in tool bar in PSoC Designer
I am unable to see program button in the tool bar in PSoC Designer 5.1 SP2
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Not yet rated
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11/02/11 |
Not using the RTC functionality in an nvSRAM with Real Time Clock
What should be the status of the RTC related pins in an nvSRAM with Real Time Clock when RTC functionality is not used?
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Not yet rated
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10/31/11 |
Cross family cloning in PD5.1 SP2 crashes PD
When I try to clone a project from one family to another in PD5.1 SP2 PSoC Designer crashes. Why is this and how can I work around it?
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Not yet rated
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10/21/11 |
Installation Hang while installing PSoC Designer 5.1 SP2
How to install PSoC Designer 5.1 SP2 when the installation hangs in between?
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Not yet rated
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10/20/11 |
PSoC3 bootloader application checksum verification bug
Why is my bootloader checksum verification failing?
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Not yet rated
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10/19/11 |
Over-Current and Non-Polarized Connection Issue with Miniprog3 *A
Are there any over-current or connection issues with the Miniprog3 *A?
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(5/5) by 1
user
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10/18/11 |
PSoC 3/5 periodic wakeup source
How can I generate a periodic wakeup in PSoC 3 or PSoC 5?
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Not yet rated
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10/17/11 |
PSoC 3 CLI commands DAP_Acquire vs Acquire
Why can I not acquire my PSoC 3 using the Acquire command?
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Not yet rated
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10/17/11 |
USB Bootloader HOST program for enCoRe III and enCore V
Is there a sample HOST program to boot load my USB device?
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Not yet rated
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10/14/11 |
Advantage of using 'BootLdrUSBFSe' user module over 'BootLdrUSBFS'
Why should I use 'BootLdrUSBFSe' user module instead of 'BootLdrUSBFS'?
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Not yet rated
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10/14/11 |
Bit Addressability of GPIO Pins in PSoC 3
How does one address individual GPIO pins of PSoC 3?
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(5/5) by 2
users
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10/13/11 |
USB Host in PSoC 3/5
Can PSoC 3/5 act as USB host?
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Not yet rated
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10/13/11 |
Flash read/write access from firmware in PSoC1 devices
How Can we read and write to flash in the PSoC1 devices?
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(4/5) by 1
user
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10/12/11 |
"Program" button not displayed on PSoC Designer toolbar
The "Program" button is not being displayed on my PSoC Designer 5.1 toolbar. How to make it appear ?
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Not yet rated
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10/12/11 |
Getting Started With the PSoC Microcontroller
How do I get started with PSoC?
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Not yet rated
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10/12/11 |
Cypress 100-Pin TQFP Land Pad Geometry
- What are the dimensions of the feet in the 100-pin TQFP package?
- What size should the pads on my board be for a 100-pin TQFP device?
- Suggestions for how to lay out board?
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Not yet rated
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10/11/11 |
Premature PCI cycle end
What happens on a premature cycle end for the PCI-DP, e.g. by making SELECT inactive before the fourth DWORD?
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Not yet rated
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10/11/11 |
Accessing Operations Registers and Shared Memory
- Are there any timing differences between the register access and shared-memory access?
- Do the same rules apply for reading and writing to the operations registers versus the shared memory?
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Not yet rated
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10/11/11 |
Arbitration register
- How is the arbitration register used in the PCI-DP?
- Does the arbitration register prevent collisions?
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Not yet rated
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10/11/11 |
External Vcc Clamps
Are external e.eV IO Clamps needed for the PCI-DP?
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Not yet rated
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10/11/11 |
Interfacing 5V dual-ports with both 5V and 3.3V processors
- Can I power the 5V dual-port with a 3.3V supply (accepting a reduction in speed)?
- I need to interface the dual-port to 5V parts and to 3.3V parts. Is this going to work safely?
- If the two processors attached to the dual-port have different I/O standards (for example, one processor is TTL and one is CMOS), can I still use your dual-port?
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(4/5) by 1
user
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10/11/11 |
Minimum / maximum read and write pulse widths
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Not yet rated
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10/11/11 |
Clearing interrupts in the Host Interrupt Event Status Register
- How do I clear interrupts in the Host Interrupt Control and Status Register?
- How do I clear interrupts in the Local Processor Interrupt Control Status Register?
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Not yet rated
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10/11/11 |
Shared memory arbitration
- How do you prevent collisions in the PCI-DP?
- Is there on-chip arbitration?
- What happens if both the local bus and the PCI bus try to access the same memory location at the same time?
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Not yet rated
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10/11/11 |
NOP cycle in Cypress Dual-Ports
- What is the NOP cycle in the Read Write Read waveform in dual-ports?
- What does NOP stand for?
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(3/5) by 2
users
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10/11/11 |
Pin to pin compatibility issues of Cypress dual-ports
In the IDT device IDT7006L25J, which is a 16K x 8 DPRAM, pins 2 and 33 are No Connect (NC) whereas the correspnding pins in CY7C006A have A14L and A14R for those pins respectively. Is the Cypress part pin-to-pin compatible?
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Not yet rated
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10/11/11 |
Accessing the EEPROM
- How to check the access the serial EEPROM attached to the PCI-DP?
- Is there a way to access (read / write) the boot EEPROM?
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(2.5/5) by 2
users
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10/11/11 |
DualPort: Using Extra Bits for Parity
- Standard bus sizes are 8-bits, 16-bits, 32-bits or 64-bits. Why are Cypress dual-ports offered in 9-bit, 18-bit, 36-bit, and 72-bit versions?
- What are the "extra" bits in the data bus used for?
- Are the extra bits parity bits?
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(4/5) by 1
user
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10/11/11 |
Memory Cell Architecture of Cypress Dual-Ports
- What is the construction of each memory cell?
- Are Cypress dual-ports "true" dual-ports?
- Are dual-port cells different than regular SRAM cells?
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Not yet rated
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10/11/11 |