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Title
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Customer Rating
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Updated
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Electrostatic Discharge Protection for CY7C68000
What does Cypress recommend for electrostatic discharge protection of the CY7C68000 part?
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Not yet rated
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06/19/11 |
Differences between the CY7C68000 and the CY7C68000A
What is the difference between the CY7C68000 and the CY7C68000A?
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Not yet rated
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06/19/11 |
CY7C68001 Operation Without an On-board CPU
Can the CY7C68001 operate an application without an onboard CPU?
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Not yet rated
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06/19/11 |
SX2 reset time and recommeded circuit
What is a good reset time for the SX2? How should the RESET be wired?
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Not yet rated
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06/19/11 |
Connecting SX2 SLOE and SLRD together
Can the two signals SLRD and SLOE specified in REVD version of the SX2 datasheet be tied together as there is no timing restriction between them.
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Not yet rated
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06/19/11 |
Reprogramming the CY24LC64 EEPROM on the SX2
How to reprogram the CY24LC64 EEPROM on the SX2 development kit board?
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Not yet rated
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06/19/11 |
Reading GPIO inputs
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Not yet rated
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06/19/11 |
SRAM to FX2LP for Memory Expansion
How can I wire an SRAM to the FX2LP device for memory expansion. Please provide a pin to pin connection detail.
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Not yet rated
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06/19/11 |
Bad Duty Cycle Fix Possibility by ZDB
Can a ZDB fix bad duty cycle?
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Not yet rated
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06/19/11 |
EPPROM Programming Software -- ISD-300A1
Is there software available to program the EEPROM for the ISD-300?
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Not yet rated
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06/19/11 |
Asserting PKTEND pin when endpoint buffer is full in FX1/FX2/FX2LP
There is a note in the technical reference that states to never assert PKTEND on a full FIFO. If I have a quad buffered system and I put the last byte into the last packet, causing FULL flag to assert (operating in manual mode) can I not assert PKTEND commit the 4th packet to USB?
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Not yet rated
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06/19/11 |
Single-Ended PECL
Can PECL inputs be driven single-ended?
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Not yet rated
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06/19/11 |
Static Discharge Voltage Test
What is the test that is used to screen Static Discharge voltage?
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Not yet rated
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06/19/11 |
Precautions when handling Op-Amp dedicated pins in a PSoC 3/5 design
What are the precautions to be taken when handling Op-Amp dedicated pins in a PSoC 3/5 design?
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Not yet rated
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06/18/11 |
Burst and NoBL SRAM access
What do you mean by 2-1-1-1 and 3-1-1-1 accesses which you show for Sync Burst and NoBL SRAMs?
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Not yet rated
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06/18/11 |
Simultaneous Reads and Writes on the CY7C1302 QDR
On the QDR SRAM, can I give a READ and WRITE command simultaneously?
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Not yet rated
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06/18/11 |
JTAG pins floating
If we do not want to use the JTAG, can we leave those pins floating?
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Not yet rated
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06/18/11 |
Capturing data with a single clock using DDR SRAMs
I am using a FPGA with a DDR interface that will support capturing data off both edges of a single clock. Can I use only one of the CQ and CQ* pairs and capture both edges?
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Not yet rated
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06/18/11 |
Effect of Speed, Package Type and Die Revisions on Models
When browsing the website for SRAM models, I have noticed that certain speeds have the same models while other models are package or revision specific. How do you know which models are affected by revisions, packages, or speed of the device.
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Not yet rated
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06/18/11 |
K and K\ signals in DDR
Are K, K\ are differential signals in DDR?
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Not yet rated
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06/18/11 |
Standby current when address lines are float
Does floating address lines in the standby mode have any effect on the standby current of the device?
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Not yet rated
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06/18/11 |
NoBL SRAM CY7C1370DV25 JTAG test
The NoBL SRAM CY7C1370DV25 issue list indicates that the part does not support boundary scan. Can I still run the boundary scan / JTAG test on a system which has this memory?
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Not yet rated
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06/18/11 |
Termination design on the Sync SRAM NoBL
What is the recommendation for the termination design for the Standard Synchronous/ NoBL SRAMs ?
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Not yet rated
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06/18/11 |
Number of cycles required to read CY7C1380 (standard Sync pipeline)
Is it possible to do an ARBITRARY NUMBER of CONSECUTIVE read access (one access per clock cycle) to a series of random locations; i.e. it is possible to use this chip to read the entire memory in 512K clock cycles?
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Not yet rated
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06/18/11 |
Parity generation during Read and Write
How is parity generated during reads and write?
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(4/5) by 1
user
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06/18/11 |
TDO Output of the JTAG circuitry
When Boundary Scan input signals are applied to TDI, TCK and TMS pins of the chip, no output signal can be detected from TDO pin of the chip. What is the problem?
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Not yet rated
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06/18/11 |
Clock enable CEN# reduces power consumption if disabled
Does Clock enable CEN# reduce power consumption if disabled (High)?
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Not yet rated
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06/18/11 |
SRAM load Conditions for given specs
What is the load to which the datasheet parameters are guaranteed for?
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Not yet rated
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06/18/11 |
necessity of clock when a ZZ pin is asserted
According to the datasheet for a Sync SRAM device, the clock is still available to the device after the asynchronous ZZ signal is asserted. Is the clock necessary? Is it possible to stop applying the clock, by tying the clock to either "1" or "0", after asserting the ZZ signal?
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Not yet rated
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06/18/11 |
SRAM Interface to Motorola 7410 Processor
What are the ranges of densities that can be used for L2 Cache application with a Motorola 7410 Processor?
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Not yet rated
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06/18/11 |
NoBL Burst and Standard NoBL differences
What are the differences between the standard NoBL and the NoBL Burst 72M SRAMs?
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Not yet rated
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06/18/11 |
NoBL Sram Definition
What is a NoBL SRAM?
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(5/5) by 1
user
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06/18/11 |
Package selection of Synch SRAMs
What are the selection criteria in selecting a package for Synchronous SRAMs?
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Not yet rated
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06/18/11 |
Sync Burst SRAM Deselect Sequence
How do we deselect a Sync Burst SRAM?
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Not yet rated
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06/18/11 |
Use of ADV/LD pin
What is the use and the function of the ADV/LD pin?
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Not yet rated
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06/18/11 |
CY2308 configuration of S1 and S2
If S2=1 and S1=0, then as per the datasheet, the output source is reference instead of PLL. What will the propagation delay be in this case?
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Not yet rated
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06/18/11 |
CY2302 Transistor Count, Technology and Gate Count
What is the technology, die size, transistor and gate count for CY2302?
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Not yet rated
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06/18/11 |
Maximum junction temperature and Theta JC thermal resistance of CY2302SXI-1 part
What are the values of Maximum junction temperature and Theta JC thermal resistance of CY2302SXI-1 part?
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Not yet rated
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06/18/11 |
CY23FS08 Input Switching Behavior with an External Mux
When an external mux is used with the need to have more that 2 inputs, do we have glitches passing from an input to another?
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Not yet rated
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06/18/11 |
UDMA Mode Support with ISD-300A1
Since ATA-34pin(CBLID#) can be used to limit UDMA mode support, should UDMA be limited to UDMA mode 2? How does the ISD-300A1 determine the device protocol?
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Not yet rated
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06/18/11 |
Maximum Input frequency for T0, T1, T2 inputs
What is the maximum frequency for the T0, T1, T2 inputs?
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Not yet rated
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06/18/11 |
eeprom.c and eeprom.h files missing in Vend_Ax example.
I recently downloaded and installed the CY3684 development kit software. When I try to build the Vend_Ax example I get an error message saying that the eeprom.c and eeprom.h files are missing. What should I do?
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Not yet rated
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06/18/11 |
Intermittent IMODE Operation Using the ISD-300.
Is Intermittent IMODE operation in ISD-300 a known bug?
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Not yet rated
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06/18/11 |
Programming the ISD-300
How to program the ISD-300?
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Not yet rated
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06/18/11 |
Bulk Command Failures with an ISD-300.
Bulk commands with a DTL of 0xFFFF will fail on UDMA devices with an ISD-300.
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Not yet rated
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06/18/11 |
Registering KEIL compiler of PSoC Creator in a PC without Internet connection
For registration of free Keil C licensing, we are required to connect to Internet through PSoC Creator tool. However, we do not have our computer connected to internet. Do we have any option to register the free Keil C license without PSoC Creator tool installed PC?
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(3/5) by 2
users
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06/18/11 |
Getting "Keil License expired" error message in PSoC Creator
When I compile project using PSoC Creator, I get following error:
"ERROR: Keil License expired. Obtain a valid Keil license and update the information through your installed version of Keil or in PSoC Creator"
How to remove this error?
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Not yet rated
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06/18/11 |
CY8CKIT-023 EBK Example Projects Build Failure with PSoC Creator 1.0 and PSoC 3 Production Silicon
How to successfully build the example projects found in "CY8CKIT-023 PSoC Expansion Board Kit For iPhone & iPod Accessories" with PSoC Creator 1.0 (and PSoC Creator 1.0 SP2 software) and the production version of PSoC 3 silicon?
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(1/5) by 4
users
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06/18/11 |
Requisite of capacitors for Vcca/Vdda to Vssa even if Analog components are not being used in PSoC 3/5
Are the capacitors from Vcca/Vdda to Vssa needed if the Analog components are not used in PSoC 3/5?
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Not yet rated
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06/18/11 |
"CYDEV_SFR_USER_CPUCLK_DIV undefined error" from PSoC Creator with PSoC 3
I'm getting "CYDEV_SFR_USER_CPUCLK_DIV undefined error" error message while updating a project to PSoC Creator 1.0 & ES3 Silicon. How to resolve it?
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Not yet rated
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06/18/11 |