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Title Customer Rating Updated
Error: File type mismatch. Attemted to put code in a codeless PROM type
When I am using 0xC0 as first byte in Hex2bix utility to generate .IIC file it gives this error: "Error: File type mismatch. Attempted to put code in a codeless PROM type."

Not yet rated
07/01/11
CY7C68013A - RESERVED pin
What should be done with the RESERVED pin #21 of 56-pin CY7C68013A?

(5/5) by 2 users
07/01/11
AT2LP has a slower HDD format time than CY7C68300A
Why AT2LP has a slower HDD format time than CY7C68300A?

(5/5) by 1 user
07/01/11
FX2LP - Difference between Port I/O, GPIF and Slave FIFO
What are the key differences between the three modes: PORT, GPIF, FIFO. Once selected you can't really switch between the three can you?

Not yet rated
07/01/11
Address line configuration setting in GPIF Designer
I am using the GPIF Designer. I use PE7 for another hardware function . I have 'right-clicked' in the Block Diagram tab and cleared the ADR8 box (the line went grey). But when I look at the gpif.c file generated I see: // Configure GPIF Address pins, output initial value, PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0] OEC = 0xFF; // and as outputs PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8] OEE |= 0x80; // and as output This seems to be setting PE7 as an output (I need it as an input). I can obviously manually edit gpif.c, but if someone modifies the design later and regenerates gpif.c this will cause a problem. Is there a way to stop GPIF Designer from affecting PE7?

Not yet rated
07/01/11
HID example for FX2 (CY7C68013)
Can I get the HID example for FX2 (CY7C68013)?

(5/5) by 2 users
07/01/11
Clarification on FX2 FIFO Full Flag behavior on OUTs
The FX2 is setup with a 512 byte, quad buffered, OUT endpoint. Would the FIFO full flags go active once a 512 byte packet is received from the host, or after 4 x 512 bytes are received from the host? An experiment with a double buffered (2x512) EP2 was done, where 2 one-byte packets were sent to it over USB. The full flag did not assert until the second byte had been placed into the second 512-byte buffer and passed to the slave side. Is this the correct behavior?

Not yet rated
06/30/11
LUN0 and LUN1 String Format
How to display the USB device name in Device Manager and the Properties windows?

Not yet rated
06/30/11
Voh of 2.4V Minimum with a 3.3V Supply (CY2292F)
Why does Cypress specify a Voh of 2.4 v min with a 3.3v supply when in fact the measurement shows a voltage exceeding 0.95 vcc (close to 3.3 v)? This device is to be used to drive a clock pin that requires the CMOS range not, the TTL 2.4 v range of level for the logic high.)

Not yet rated
06/30/11
Algorithm For Calculating P & Q values
How can I calculate optimal P and Q counter values for the CY22150 without using CyberClocks?

Not yet rated
06/29/11
Serial Programming PLL1 Frequency Changes In The CY22393/4/5
How can I serially program frequency changes into PLL1 of the CY22393/4/5?

Not yet rated
06/29/11
Changing The Default SPI Address
What is the low-level SPI procedure for changing the default address from 69H to another value?

Not yet rated
06/29/11
Output Voltage Range Possibility for CY22800
How can a varying output voltage of 1 to 5.5 volts be implemented?

Not yet rated
06/29/11
CY22381 Frequency Ranges
What are the minimum and maximum frequency ranges for the CY22381?

Not yet rated
06/29/11
CY22394 Frequency Ranges
What are the minimum and maximum frequency ranges for the CY22394?

Not yet rated
06/29/11
Crystal Drive Level for The CY22050.
What is the crystal drive level is for the CY22050 clock generator?

Not yet rated
06/29/11
Eight Different Values Programming Possibility in CY22394
It is possible in the CY22394 to select eight different values of the frequency of PLL 1 using the start-up values of S0, S1 and S2. However, is it possible to program them to flash using software?

Not yet rated
06/29/11
CY22393 Frequency Array Table: 8x3 registers Register Requirement
Why does the SONOS Frequency Array Table of part CY22393 include 8x3 registers for the configuration of the PLL1 (40h to 57h) when S2 has only 2 bits? The 4x3 registers seem to be sufficient (40h to 4Bh).

Not yet rated
06/29/11
Jitter Specification of the CY22800FXC
We have different configurations so what is the typical ans maximum jitter?

Not yet rated
06/29/11
Crystal Specifications for the CY22381
What are the specifications that should be looked at when we select a crystal of a particular frequency we need for CY22381?

Not yet rated
06/29/11
Serial Programming Sequence in CY22393/4/5
What is the programming protocol or sequence for the CY22393/4/5?

Not yet rated
06/29/11
Default Device Address in CY22393/4/5
What is the default device address for serial programming of CY22393/4/5 devices?

Not yet rated
06/29/11
Programming the CY22150 with FPGA
When using an FPGA on a PCB for serial programming of the CY22150, during write mode, the device will respond with an ACK pulse after eight bits by pulling the SDAT line low. Is this a 'weak 0', or a 'strong 0'? Can there be a conflict with the I/O of the FPGA?

Not yet rated
06/29/11
Skew from External Clock with CY22381
What is the skew of the output from an external input clock with the CY22381?

Not yet rated
06/29/11
Need for Different Checksums for CY2292 JEDEC Files
Why are there different checksums for JEDEC files on the CY2292F?

Not yet rated
06/29/11
Validity of Input Frequency Change without Jedec File Change for CY25100
Can we change the reference frequency without reprogramming the CY25100?

Not yet rated
06/29/11
External Crystal Load Capacitor Requirement for the CY22381
Can we have external load capacitors while using a crystal as a reference input for the CY22381?

Not yet rated
06/29/11
Programming Tools Options for the CY22801
What are the programming tools available for programming the CY22801?

Not yet rated
06/29/11
Possibility of CY22801 as a Zero Delay Buffer (ZDB)
Can the CY22801 maintain the phase between the input and the output and act as a Zero Delay Buffer?

Not yet rated
06/29/11
Field Programmability for CY2081
Is the CY2081 field programmable?

Not yet rated
06/29/11
Unprogrammed Device Outputs For The CY2907
What are the clock output frequencies on an unprogrammed CY2907?

Not yet rated
06/29/11
CY2292 Device Weight
How much does a CY2292 16-pin SOIC weight?

Not yet rated
06/29/11
Loop Bandwidth of CY2291/CY2292
What is the loop bandwidth of a CY2291 or CY2292?

Not yet rated
06/29/11
Negative Resistance of CY2291 / CY2292
What is the negative resistance of the crystal oscillator on the CY2291 or CY2292?

Not yet rated
06/29/11
Unprogrammed Device Outputs of CY2291/CY2292
What are the clock output frequencies on an unprogrammed CY2291 or CY2292?

Not yet rated
06/29/11
PLL Lock Time of CPLL in CY2291/CY2292
Why does the CPLL on the CY2291 or CY2292 have a longer lock time than the UPLL or SPLL?

Not yet rated
06/29/11
Output Clock Phase Alignment for CY2291/CY2292
Are the clock outputs of the CY2291 or CY2292 phase aligned?

Not yet rated
06/29/11
Programming Flash Memory In The CY22393/4/5
How many times can the CY22393/4/5 be programmed?

Not yet rated
06/29/11
SE0's generated by the CY7C65100 and Other M8 Full Speed Chips
What causes the CY7C65100 to generate many SE0's on the upstream bus?

Not yet rated
06/29/11
Programming Flash Memory Times of CY22150
How many times can I program the CY22150?

Not yet rated
06/29/11
Peak-to-Peak Jitter in The CY22381
What is the typical jitter value for CY22381?

Not yet rated
06/29/11
Peak-to-Peak Jitter of CY22050
What is the typical jitter value for the CY22050?

Not yet rated
06/29/11
Data I/O Programming for the CY22381
Does the CY22381 support DATA I/O programming?

Not yet rated
06/28/11
Voltage Levels for CMOS XTAL Inputs, CY2292
What are the acceptable voltage levels for the CMOS XTAL inputs?

Not yet rated
06/28/11
When a port data register (I/O Address 00H, 01H, 02H, 03H) is written and then immediately read back, why are the values different?
When a port data register (I/O Address 00H, 01H, 02H, 03H) is written and then immediately read back, why are the values different? This question applies to: CY7C64013, CY7C64113, CY7C65013, CY7C65113, CY7C66013, CY7C66113.

Not yet rated
06/28/11
Unused serial inputs and outputs on HOTLink CY7B923/CY7B933
What should be done with unused serial inputs and outputs on HOTLink CY7B923/CY7B933?

Not yet rated
06/28/11
Adding the more icons to the toolbar in PSoC Designer

Not yet rated
06/28/11
Semaphore Value in Asynchronous Dual-Ports
- What are the uses of Semaphore latches? - How are semaphore values read on the I/O bus?

Not yet rated
06/27/11
When code compiled with the ByteCraft C compiler is loaded into CYDB not all of the debugging features are functional
When code compiled with the ByteCraft C compiler is loaded into CYDB, not all of the debugging features such as breakpoints and single stepping are functional.

Not yet rated
06/27/11
When developing a USB hub with the CY3654+P03 development kit why don't any devices show up in the device manager
When developing a USB hub with the CY3654+P03 development kit why don't any devices show up in the device manager when plugged into the downstream ports?

Not yet rated
06/27/11
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