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Title
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Customer Rating
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Updated
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Using the CY4601 reference design at 115K baud.
Does the CY4601 reference design support a baud rate of 115.2K baud?
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Not yet rated
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01/01/12 |
I/O using SFRs in the AN2131
Are there any example projects available to access the SFR registers to implement the 8051's I/Os in AN2131QC.
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Not yet rated
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01/01/12 |
Custom boot.tpl. from PD 4.3 to PD 4.4
As of 4.3 I was able to extensively customize our boot.tpl files. However, in Psoc Designer 4.4 when I open the project it wants to create a new boot.tpl. If I let it, of course I lose my custom boot.tpl. If I click Cancel, it lets me keep it but refuses to do the "generate application" step. OK, I've noticed that I can re-enable the button by editing the project settings. How to solve this problem?
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Not yet rated
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01/01/12 |
two rings surrounding thermal pad of CY8C20434-12LKXI (32 QFN)
There are two rings surrounding the thermal pad on the bottom of the chip. Is it safe if they are all connected together (soldered in manufacturing)?
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Not yet rated
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01/01/12 |
Running the debugger on a custom board without external memory AN2131
Is it possible to run the debugger on the AN2131S, since it does not have external memory?
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Not yet rated
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01/01/12 |
OrCAD PCB Libraries
Need PSoC Orcad Library
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Not yet rated
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01/01/12 |
ezusbw2k.inf modification for AN2131
What resources are available to modify the ezusbw2k.inf file?
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Not yet rated
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01/01/12 |
Interrupt Service Routines example for EZ-USB
Are there any code example that demonstrates configuring ISRs?
Are there any host application examples that demonstrate handling ISRs?
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Not yet rated
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01/01/12 |
Clear a Pending Interrupt
Section B:5 'Interrupt Controller' of the Technical Reference Manual says that an interrupt stays pending until it is serviced. What needs to be done to 'service' the interrupt? Also, what is it that actually clears the pending interrupt?
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Not yet rated
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01/01/12 |
Clearing the INTOUTn line from a GPIO cell
If I have an interrupt on edge, what clears the Interrupt Output (INTO) line from the GPIO cell?
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Not yet rated
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01/01/12 |
AN2131 UART Function
Why does the UART continuously shift out the same data byte until a new byte is loaded?
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Not yet rated
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01/01/12 |
Confirmation of AN2131 Dual Data Pointer operation
The DPS register selects whether the usual DPH0/DPL0 pair is active or whether DPH1/DPL1 is active. However, this concept doesn't seem to work for all DPTR-related instructions, particularly the register load instructions. The following code illustrates the problem (it is a fast copy routine, with pointers to source and destination, a byte count in R3):
mov DPS,#0 ;initialize the DPS reg (1)
mov DPH,R4 ;load destination pointer from R4, R5 (2)
mov DPL,R5 ;R5 has low pointer (3)
inc DPS ;switch data pointers (4)
mov DPH,R6 ;load source ptr from parms in R6, R7 (5)
mov DPL,R7 ;R7 has low pointer (6)
loop:
movx A,@DPTR ;get byte from source pointer (8)
inc DPTR ;advance the source pointer (9)
inc DPS ;switch to destination pointer (10)
movx @DPTR,A ;store byte in destination (11)
inc DPTR ;advance destination pointer (12)
inc DPS ;switch back to source pointer (13)
djnz R3,loop ;decrement count, loop back for more (14)
ret ;done (15)
The problem occurs in lines 5 and 6. Even though there was an instruction in line 4 to switch to the other data pointer (inc DPS), the statements in lines 5 and 6 appear to overwrite special function register addresses 82H and 83H, not 84H and 85H. In other words, even though you might think that the second data pointer is the active data pointer, instructions that reference DPH and DPL always refer to the first (DPH0/DPL0) data pointer. In order to initialize the second data pointer (DPL1 and DPH1) properly, one must explicitly reference DPL1 and DPH1. Thus lines 5 and 6 must be coded as:
mov DPH1,R6 ;load source ptr from parms in R6, R7 (5)
mov DPL1,R7 ;R7 has low pointer (6)
This seems to work. How can this problem be explained?
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Not yet rated
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01/01/12 |
Getting error message: "cannot detect a pod"
I am getting error message: "Cannot detect a pod". How to remove it?
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(4/5) by 1
user
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01/01/12 |
Fast transfer feature of the EZ-USB AN2135SC - FRD#, FWR# lines not toggling
The FRD# and FWR# lines are not toggling on the AN2135SC if the absolute address is 0xF000 or 0x8051 (outside the on-chip RAM space). The PORTACFG bits, FRD# and FWR# line signals, and data lines D0-D7 are correctly set.
Is this a documentation problem or does the FRD# and FWR# lines not work on devices without the external address bus?
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Not yet rated
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01/01/12 |
Breakpoint trigger code
The renumerating examples for the AN2131 and FX all have code that sets the breakpoint to trigger on TD_Poll().What does this code do and is it necessary?
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Not yet rated
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01/01/12 |
Writing data into buffer when BUSY bit is set
The EZ-USB TRM page 6-2, states that the 8051 should never read or write an endpoint buffer or byte count register while the endpoint's busy bit is set. If I write "IN2BUF[i]=..." without checking the Busy bit,what will happen if the Busy bit is still 1? Will it overwrite the buffer? Or Is the new data not written into the buffer?
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Not yet rated
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01/01/12 |
Firmware download using EzLoader
What is the basic procedure that the EzLoader driver uses to download firmware to the EZ-USB AN21xx device?
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Not yet rated
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01/01/12 |
RW /WR pins on AN2135S
Do the RW/WR pins on the AN2135S function the same way as described for the AN2131Q?
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Not yet rated
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01/01/12 |
MiniProg won't program PSoC with MAX232 on SDATA line
Unable to program PSoC with MiniProg when MAX232 is connected on SDATA line
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Not yet rated
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01/01/12 |
Recommended frequency for enCoRe III CY7C64215 to run the CPU at 3.3V
What is the recommended frequency for enCoRe III CY7C64215 to run the CPU at 3.3V ?
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Not yet rated
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01/01/12 |
USB impact when running enCoRe III at 5V versus 3.3V
EnCoRe III can run off of 5V down to 3.3V. How does the USB block handle this, and are there any differences when operating at different voltages?
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Not yet rated
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01/01/12 |
Out-of-system programming options for enCoRe III
What are the out-of-system programming options for enCoRe III?
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Not yet rated
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01/01/12 |
Why does the HID example for enCoRe III (CY7C64215) in the example section of PSoC Designer never go into suspend?
Why does the HID example for enCoRe III (CY7C64215) in the example section of PSoC Designer never go into suspend?
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Not yet rated
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01/01/12 |
Using embedded assembly with Keil micro vision
What is the syntax to follow to enable coding in Embedded assembly with the Keil micro vision tools?
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Not yet rated
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01/01/12 |
Pull-up resistor in enCoRe III
What is the actual value of the D+ pull-up resistor in enCoRe III?
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Not yet rated
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01/01/12 |
Can I program enCoRe III through the USB connector just like enCoRe II?
Can I program enCoRe III through the USB connector just like enCoRe II?
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Not yet rated
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01/01/12 |
Why does my application fail when I run the enCoRe III CPU at 24MHz (SysClk/1), but pass at 12MHz(SysClk/2)? Are there any issues with running enCoRe III at 24MHz, is there a workaround for the issue?
Are there any issues with running enCoRe III at 24MHz? (or) My application fails when I run the enCoRe III CPU at 24MHz (SysClk/1), but passes at 12MHz(SysClk/2)
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Not yet rated
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01/01/12 |
Handles to a Device using EZUSB.sys in an application
When I make calls to the EZUSB General Purpose Driver (EZUSB.sys) and get a handle to EZUSB-0, I notice that I need to get a new handle to EZUSB-1 to perform IOCTL_bulk_writes. Why does this occur?
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Not yet rated
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01/01/12 |
Reset of AN21xx chip using DISCON while connected to host
Why does the host computer not recognize the reset of connected AN21xx chip? The driver is not unloaded and the device does not reload its firmware.
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Not yet rated
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12/31/11 |
Slightly High FX2 Drive Levels on Test J or Test K
When performing the Test J or Test K test mode commands, the D+ and D- lines are measured to be 448 mV when asserted and 11 to 12 mV when de-asserted. I have a captive (tethered) cable design and measurements were made at a termination fixture at the end of the cable. When measuring the D+ and D- traces on the board itself, the voltage levels pass in the high state, but barely (438mV and 2-4mV). Why is the drive level so high?
Does the USB-IF allow the Test J/K voltage levels to be measured from the board directly, or must they be measured at the far end of the captive cable?
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Not yet rated
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12/31/11 |
FX2 WAKEUP# pin
Is the FX2 WAKEUP# pin edge or level triggered? If it is asserted, how long does it need to remain in this state for triggering a wakeup signal.
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Not yet rated
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12/31/11 |
EZ-USB General Purpose Driver
The EZ-USB General Purpose Driver says that an IOCTL_Ezusb_RESETPIPE call must be made before starting Isochronous read/write operations. Is this due to a quirk in the ezusb.sys driver or a bug in the chip? Also, should there be a delay between the pipe reset and the Isochronous read/write? If so, how long?
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Not yet rated
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12/31/11 |
Hung state on FX2 due to I2C STOP Bit
Why does the FX2 firmware hangs when the STOP bit is set after polling for the STOP bit.
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Not yet rated
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12/31/11 |
Configuring the Device to use external memory
Why should the program be loaded into the external memory prior to starting the device, when the development board is configured to have low memory?
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Not yet rated
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12/31/11 |
USB Core to 8051 interaction
Is a NAK issued by a host for a Bulk In packet reported by the USB core to the 8051 in AN21xx EZ-USB or CY7C646xx EZ-USB FX.
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Not yet rated
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12/31/11 |
JEDEC file for PLD
Where can the JEDEC file for the PLD be found?
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Not yet rated
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12/31/11 |
Discard data loaded in BULK-IN buffer AN2131
During a multiple-packet BULK-IN data transfer, the Host wants to cancel the transfer. Is there a way to discard the data packet already been loaded into the BULK-IN buffer? The problem is that the INxBC has been loaded with count of bytes in the INxBuf, but the Host stops issuing IN-Tokens until the cancellation completes. If that data packet is not cleared, the Host will read it as obsolete/incorrect data after the cancel. According to the TRM, it looks like the BUSY bits in INxCS is cleared by the EZ-USB core. Is there a way/procedure to reset the BUSY bits in INxCS in the program?
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Not yet rated
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12/31/11 |
Input Clock Jitter using 12Mhz clock
What is the Input Clock Jitter using a 12Mhz Clock for EZ-USB AN2131?
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Not yet rated
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12/31/11 |
I have an EZ-USB AN21xx device and I'm trying to do overlapped i/o for the DeviceIoControl call and it is performing ...
Does EZUSB.sys support overlapped I/O?
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Not yet rated
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12/31/11 |
Using 8051 interrupt service routines along with the USB interrupts
How to create separate 8051 Interrupt Service Routines along with the USB interrupts?
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Not yet rated
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12/31/11 |
What is Dynamic Reconfiguration?
What is dynamic reconfiguration?
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Not yet rated
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12/31/11 |
Object Not Supported Error
How do I fix the error message: "Object doesn't support this property or method?"
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Not yet rated
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12/31/11 |
Internal version of ezmon.sys
Can the monitor driver be rebuilt to load an internal version of the monitor instead of the default version that loads to external memory?
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Not yet rated
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12/31/11 |
Malloc function
Does compiler in PSoC designer support memory allocation functions like malloc?
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Not yet rated
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12/31/11 |
Powering the AN2131 Development board
Does the AN2131 development board require an external power supply?
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Not yet rated
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12/31/11 |
Use of Port B for Data bus while using INT1 pin from Port C
I want to use the INT1 pin as a strobe (for example when the converter samples, it sends the strobe to the core and it reads the byte and sends it), but the INT1 pin is on PORT C, so I can't use all 8 port C pins as I/O pins. Which pins should I use to get the byte of data? Can I use the 8 8051 data bus pins and how?
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Not yet rated
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12/31/11 |
Distributing General purpose driver (ezusb.sys) with a custom product
Can the Cypress general purpose driver,ezusb.sys be distributed along with a Custom Device?
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Not yet rated
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12/31/11 |
Variable accessible by ISR and Main code
How can a variable that can be accessed by both the idle loop ( in TD_Poll ) and also by a USB ISR be implemented such that, if it is being accessed by TD_Poll, ISR is not able to manipulate it until TD_Poll finishes and vice-versa.
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Not yet rated
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12/31/11 |
Assertion of INT0# pin on FX does not trigger an Interrupt
For how long the INT0# pin should be asserted for an interrupt event to be detected?
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Not yet rated
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12/31/11 |
High-capacitance load on CLKOUT pin of FX2LP
My design interfaces a high-capacitance load to the CLKOUT pin of FX2LP. I’m not sure about the effect on the rise-time and fall-time of the signal due to this. How do I evaluate whether I can directly interface with the pin or if I should add a buffer on the line?
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Not yet rated
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12/31/11 |