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Title
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Customer Rating
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Updated
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SPLDs for New Designs
If I am designing a new design using an SPLD, which one should I use?
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Not yet rated
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01/01/12 |
Use of the CEO/A2 in a Single Chip Configuration
What do I do with the CEO/A2 pin if I only use one EEPROM?
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Not yet rated
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01/01/12 |
Functionality Problem with Ultra37000V CPLD Despite Passing Simulation
1. A pin gets pulled low even though the simulation shows it correct?
2. I get daisy chain errors, why?
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Not yet rated
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01/01/12 |
Hysteresis on Input of Cypress Quantum38K CPLDs
Do Quantum38K CPLDs have hysteresis on the inputs?
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Not yet rated
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01/01/12 |
Are military parts vacuum sealed?
Are military parts vacuum sealed?
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Not yet rated
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01/01/12 |
Issues with Pins Locked to a Certain Level Despite Simulation
1.I have a pin that is unresponsive despite all attempts to drive the signal?
2.The functional simulation shows that it should work, but it doesn't. Help?
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Not yet rated
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01/01/12 |
Why tS > tSPT for Ultra 37000 CPLDs
Why is tS > tSPT?
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Not yet rated
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01/01/12 |
Thermal Information for Cypress Flash370i CPLDs
1. What is the Theta JA value for the 37xi?
2. What is the Theta JC value for the 37xi?
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Not yet rated
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01/01/12 |
Differences Between Revision A and Revision B of Ultra 37000 CPLDs
Ultra37000, Ultra 37k, 37k, 37000, 37032, 37064, 37128, 37192, 37256, 37384, 37512 revision, silicon, rev, die, change, update
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Not yet rated
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01/01/12 |
ISR Failures during Flash 370 and Flash 370i Programming
Why is ISR failing programming?
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Not yet rated
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01/01/12 |
Boundary Scan on Flash370 and Flash370i CPLDs
Can I perform a boundary scan on the Flash 370 and Flash 370i devices?
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Not yet rated
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01/01/12 |
Transparent Latches in Ultra 37000 CPLDs
Can I implement a transparent latch in an Ultra 37000 device?
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Not yet rated
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01/01/12 |
Security Bit in the Ultra 37000
1. What does the security bit do?
2. How do I set the security bit?
3. Can I recover a design from a device programmed with the security bit?
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Not yet rated
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01/01/12 |
Do MAX340 EPLDs Have Internal Oscillators?
Do MAX340 EPLDs Have Internal Oscillators?
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Not yet rated
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01/01/12 |
In Aldec-HDL is there any way to name remerged signals other than VBUS#
In Aldec-HDL is there any way to name remerged signals other than VBUS#?
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Not yet rated
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01/01/12 |
Creating Bi-Directional Signals in Warp
1.How do I create a bidirectional signal in Warp?
2.How do I correctly simulate a bidirectional signal?
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Not yet rated
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01/01/12 |
Is there an application to convert a *.stp or *.hex file into a C code array?
Is there an application to convert a *.stp or *.hex file into a C code array?
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Not yet rated
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01/01/12 |
Registering Warp
1.How do I register Warp?
2.Where is the online registry area?
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Not yet rated
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01/01/12 |
Why does the ISR software not show a particular revision of Delta 39K devices?
Why does the ISR software not show a particular revision of Delta 39K devices?
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Not yet rated
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01/01/12 |
BSDL model of CY37032P44 device
Where can I find BSDL model of CY37032P44 device.
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Not yet rated
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01/01/12 |
Avoiding overflow of RX FIFO in the CY7C924ADX and CY7C9689A.
How to avoid RX FIFO overflow in the CY7C924ADX and CY7C9689A?
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Not yet rated
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12/07/11 |
Characteristics and considerations for HOTLink jitter
What are the characteristics and considerations for HOTLink jitter?
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Not yet rated
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12/07/11 |
Data stream is always valid when RVS is LOW
Is it guaranteed that the data stream is always valid when RVS is LOW?
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Not yet rated
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12/07/11 |
Application note : Driving Copper Cables with HOTLink™
Where can I donwload the Application Note "Driving Copper Cables with HOTLink™"?
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Not yet rated
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09/15/11 |
Moisture Sensitivity Level (MSL) of Cypress Parts
How do I find Moisture Sensitivity Level (MSL) of Cypress parts?
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Not yet rated
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09/08/11 |
Interfacing the SO pin to CY7B933
If the SO pin is pulled up (the SI input now becomes the INB- input), and at a later time this pull up is removed (after device interface configuration) does the SO become an output of the SI signal?
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Not yet rated
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07/01/11 |
Are the FIFO's accessible (for either reads or writes) when the part enters BIST mode (CY7C924ADX or CY7C9689A)
1)Can I read characters from the RXFIFO during BIST mode (CY7C924ADX or CY7C9689A)?
2)Can I write characters to the TXFIFO during BIST mode (CY7C924ADX or CY7C9689A)?
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Not yet rated
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07/01/11 |
MTBF or FIT of the CY7B923/CY7B933
What is the MTBF or FIT of the CY7B923/Cy7B933?
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Not yet rated
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07/01/11 |
Is there a drop in replacement for the Cy7B923/933 LMB military package
1)Is there a drop in replacement for the Cy7B923/933 LMB military package?
2)Can I replace the Cy7B923/933-LMB with a -JC or -JI?
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Not yet rated
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07/01/11 |
Configure the HOTLink 1 for 3.3V I/O?
Is there a way to configure the HOTLink 1 for 3.3V I/O?
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Not yet rated
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07/01/11 |
SMPTE standards supported by HOTLink family
1)How can I use the HOTLink1 parts in a SMPTE-259M application?
2)Does Cypress have a part that supports the SMPTE 310M video standard?
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(4/5) by 2
users
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07/01/11 |
Should I use HOTLink CY7C924ADX or CY7C9689A
Should I use HOTLink CY7C924ADX or CY7C9689A?
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Not yet rated
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07/01/11 |
Configuration of the Status In (SI) and Status Out (SO) Pins
1) If I want to use the SO pin as a true output of SI, but the signal it is connected to is pulled up to Vcc during startup, will this affect the configuration of SO?
2) Can I change the state of SO is used during operation?
3) How is the function of the INB(INB+) input and the SI(INB-) input defined?
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Not yet rated
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07/01/11 |
Can the FIFO be bypassed in CY7C924ADX when using the byte-packer
Can I bypass the FIFO in CY7C924ADX when I want to use 10-bit encoded mode?
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Not yet rated
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07/01/11 |
Unused serial inputs and outputs on HOTLink CY7B923/CY7B933
What should be done with unused serial inputs and outputs on HOTLink CY7B923/CY7B933?
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Not yet rated
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06/28/11 |
CY9266 Evaluation Board documentation
1)How do I test the CY9266 evaluation board?
2)What types of evaluation boards are available for testing the CY7B923/CY7B933?
3)How do I setup BIST on the CY9266 evaluation board?
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Not yet rated
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06/27/11 |
Meaning in datasheet, when it says that you can write to the FIFO from DC to 50 MHz
What does the datasheet mean when it says that you can write to the FIFO from DC to 50 MHz?
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Not yet rated
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06/24/11 |
Reducing Power Dissipation: Unused serial outputs on CY7C9689
What do I do with the unused serial outputs OUTA±/OUTB± on the CY7C9689 device? Is there a setting that is particularly beneficial?
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Not yet rated
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06/24/11 |
Transformers recommendation for HOTLink CY7B9234 and CY7B9334
What transformers does Cypress recommend for HOTLink CY7B9234 and CY7B9334?
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Not yet rated
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06/24/11 |
Latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver.
What is the latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver?
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Not yet rated
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06/24/11 |
Rad hardness, Soft Error Rate (SER), Single Event Upset (SEU) rates for the CY7B923 and CY7B933.
What information do you have about rad hardness, Soft Error Rate (SER), Single Event Upset (SEU) rates for the CY7B923 and CY7B933?
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Not yet rated
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06/24/11 |
CKR outputs are unusable when the serial inputs to the CY7B933 are left floating and a REFCLK of 40MHz is supplied.
When the serial inputs to the CY7B933 are left floating and REFCLK of 40MHz is supplied,Why are CKR outputs are unusable?
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Not yet rated
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06/24/11 |
SPDSEL and RANGESEL for 100MBaud (CY7C9689A, CY7C924ADX)
1) What would be the setting on the SPDSEL and RANGESEL, if the chip has to be operated at 100 MBaud? The speed may vary above or below 100 Mbaud and Refclk would be 20 MHz?
2) -Do you recommend a spread sprectrum clock?
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Not yet rated
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06/22/11 |
HOTLink II Three Level Control Inputs
Can the 3-Level select static control inputs be controlled by an FPGA/CPLD output?
(For CYP(V)15G0401DXB, CYP(V)15G0402DXB, CYP(V)15G0201DXB, and CYP(V)15G0101DXB).
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Not yet rated
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06/13/11 |
Switching between Serial Differential Inputs
- How long does it take for HOTLInk II receiver to switch between the serial differential inputs from IN1(+/-) to IN2(+/-)
- How long does it take for HOTLInk II receiver to switch between the serial differential inputs from IN1(+/-) to IN2(+/-)
- IN1(+/-) is coming from an external link. OUT2(+/-) loop back's to IN2(+/-). Two channels have the same freq. Before the external link is established, we select IN2. We have plenty of time for the receiver to lock in IN2. When the external link on IN1 becomes OK, we switch the receiver to IN1. How long does it take for the clock recovery to lock in? Does it still take 376K UI?
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Not yet rated
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06/13/11 |
Considerations in Interfacing HOTLink II to Fiber Optic Module
What are the considerations in Interfacing HOTLink II to Fiber Optic Module? How can I interface a SFP fiber optic module with HOTLink II?
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Not yet rated
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06/13/11 |
Receive Status Bits in HOTLink II
What is the purpose of receive status bits in HOTLink II? What is the function of priority in table 20 of the data sheet of CYP15G0401DXB? What are the different modes of status reporting?
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Not yet rated
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06/13/11 |
State of the RXSC/D* signal while VLTN is asserted for the CY7C9689A
What is the state of the RXSC/D* signal while VLTN is asserted for the CY7C9689A?
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Not yet rated
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06/13/11 |
Significance of HOTLink claim of requiring no external PLL components?
What is the significance of the HOTLink claim of requiring no external PLL components?
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Not yet rated
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06/13/11 |
Power consumption of the SMPTE 259M Scrambler/Controller and Descrambler/Framer-Controller
What is the typical power consumption of the SMPTE 259M Scrambler/Controller and Descrambler/Framer-Controller?
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Not yet rated
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06/13/11 |