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Cypress offers various high-performance solutions for cellular phone designs. Cypress's West Bridge Antioch peripheral controllers and MoBL-USB families of products satisfy the need for High Speed USB. Combining world class performance and ultra-low power in a tiny package.

Our Memory portfolio provides the lowest-power static RAMs (SRAMs) in the market (densities from 1 Mb to 16 Mb) along with a wide array of pseudo SRAMs (PSRAMs) for those applications requiring more density. We offer several interface options, including CellularRAM(TM), and densities from 2 Mb to 64 Mb. Our CMOS image sensors provide the best image quality in the industry by taking advantage of our Autobrite(TM) technology and over twenty years of CMOS image sensor design experience.

Resources

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Results 1 - 11 of 11
Title Customer Rating Updated
CapSense Best Practices
The topics covered include an overview of sensing methods, guidelines for layout and assembly, and CapSense tools and techniques.

(4.3/5) by 4 users
01/14/10
Wireless Voice Audio
In the CyFi Streaming Voice Audio Solution, the PSoC works in conjunction with the 2.4 GHz CyFi Wireless Transceiver and a Nuvoton Audio Codec.

(5/5) by 1 user
12/16/09
Image Sensor Handling and Best Practices
This application IP describes methods for handling, storing, and cleaning image sensors.

Not yet rated
12/15/09
Infrared Proximity Detection with PSoC
This application IP describes the interface and signal processing for infrared proximity detection using PSoC.

Not yet rated
12/15/09
Interfacing ADMUX SRAM Processors to West Bridge Antioch
This application IP discusses how a system processor can interface to Antioch.

Not yet rated
12/15/09
CapSense(TM) Buttons with CSD
This application IP presents a basic design process to create CapSense buttons using the CSD User Module and PSoC.

Not yet rated
12/15/09
Using a USB Switch with West Bridge Antioch
This application IP discusses the implications of adding a USB switch with West Bridge Antioch, and provides the PCB layout recommendations to avoid degradation of signal integrity.

Not yet rated
12/15/09
Real-Time Clock in PSoC
This application IP describes how the PSoC Mixed-Signal Array is capable of providing the functionality of a Real Time Clock and presents the assembly language code that implements the function.

Not yet rated
12/14/09
External EEPROM Firmware Load for West Bridge Astoria
This application IP discusses how to load the Astoria firmware using an external EEPROM.

Not yet rated
12/10/09
Optimizing Performance using West Bridge(R) Controllers with Turbo-MTP
This application IP discusses West Bridge Turbo-MTP.

Not yet rated
12/10/09
Interfacing TI OMAPV1030 Processor to Astoria's Pseudo-NAND Processor Port
Cypress West Bridge Astoria provides high speed USB peripheral and mass storage control capabilities to the system processor through its host processor port.

Not yet rated
08/17/09
Results 1 - 11 of 11