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NVSRAM CY14B104NA Single Event Upset - Multi Bit Upset mitigation query
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NVSRAM CY14B104NA Single Event Upset - Multi Bit Upset mitigation query

Andy J posted on 29 Nov 2010 7:43 AM PST
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2 Forum Posts
A popular on-line encyclopedia page informed me that memory device manufacturers protect against MBUs affecting single words by having the cells organised so that physically adjacent cells are not part of a single word of memory. Thus a MBU appears as multiple Single Bit Upsets in different words in RAM. The article did not detail whether this was only a practice associated with ECC memory. Using non-ECC memory, I plan to use three copies of "SEU protected" data, and want to align the blocks to ensure that an MBU does not identically affect two of the copies. Where can I learn about the memory layout of the particular part I am using - CY14B104NA - so that I can align the blocks with care and avoid MBUs causing an identical corruption in two of my copies?


Re: NVSRAM CY14B104NA Single Event Upset - Multi Bit Upset mitigation query

Andy J posted on 15 Dec 2010 05:38 AM PST
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2 Forum Posts
Through the Cypress MyCase assistance, I was supplied with a .pdf detailing the device topology and showing the translation of External Address lines A0 to A17 with Internal Row and Column Address lines. Address changes that just affect the lsbit of the Internal Column Address and/or just the lsbit of the Row Address result in addressing physically adjacent memory. For this device, addresses that differ by just Address Lines 0 and 9 are physically adjacent memory locations. As in my case, others may need to consider the external bus mapping to their processor interface, as, particularly using this 16-bit wide part, it is possible that the processor has an AD(0) line that may not be mapped to this device.




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