You seem to be calling the internal "write latch" which gets set whenever a write happens, as dirty bit. Which implies that you want to write into the SRAM but you do not want the written data to be Stored when HSB/ is asserted. If this is what you desire, is there any reason you cannot leave the HSB/ open?
Also, why is the application disabling AutoStore at every power up. You can do it once and do a SW store to make it endure power cycles. Fom then on, Stores will happen only when you do a software Store (HW store if HSB is asserted when write has happened).
I have placed my answers to your questions inline marked ##.
Q: The datasheet for the CY14B256LA mentions 20-year data retention. Other nvSRAM products list 100 years. Is that 20 years from the most recent store operation, or 20 years total over the life of the chip?
## The 20 year data retention in the CY14B256LA is guaranteed at 85C. The 100 years in the old technology part (0.8u parts) is guaranteed at 55C. If comparison is made at the same temperatures, the new parts have 4 times the data retention of the older part.. We have stated this in the app note AN55662.
## The data retention is over the life of the part. 20 years is the accumulated data retention time.
Q: Is there any way of reading the option status from the chip?
If AutoStore is disabled, does disabling it again count as a write as far as the life of the chip goes? For example, if the device containing the chip automatically disables AutoStore every time it turns on, does each disable operation contribute to "wearing out" the chip by eating into the 1,000,000 store count?
## Unfortunately there is no way to check the enable/disable status of AutoStore in a part.
## AutoStore disabling does not count as a write nor does it affect the 1M store count.
- Autostore anable or disable is done through a specific sequence of reads. There is no write cycle involved.
- Read/write cycles are done to the SRAM portion of the nvSRAM. The SRAM has infinite read/write endurance.
- Only Store cycles count for endurance. Since you are disabling autostore, I assume you will be performing a software store or hardware store when you want to save the data to NV portion of the nvSRAM. Only those stores will count for endurance.
Q: Does disabling AutoStore set the chip's "dirty bit" thus causing a store when /HSB is asserted?
## No. As discussed earlier, the write latch is not set when you perform reads. I assume you are considering the internal write latch as "dirty bit" though I do not understand why you consider it so. The internal write latch is what prevents unwanted Store when there is no writes (and thus no change in the content). I assume you do not want Store to happen when HSB/ is asserted. If so, Store will not happen if you have performed only reads. However, if you have done writes, and do not want data to be Stored, you need to ensure HSB/ is not asserted. Or, you can leave HSB/ open.
If the dirty bit is set, are ALL bytes stored when /HSB is asserted, or only those bytes whose SRAM value differs from its stored value? “
## When Store happens it will happen to ALL bytes. The Store process consists of erasing the complete NV memory and storing the complete SRAM content into the NV memory.
Ravi, nvSRAM Apps Manager