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error in datasheet?????

Summary: 6805 Views, 1 Replies, Latest reply by psr on 24 Jun 2011 01:45 AM PST

Verified Answers: 0

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appavito posted on 22 May 2010 12:39 AM PST
Member
2 Forum Posts

we try to use CY14B101P memory with SPI and RTC in AUTOSTORE MODE. on product datasheet at page 3 in table 1 Pin definition the CS pin active the device when is pulled low (GND?? or not connected??). BUT at page 5(of34) on FIgure n.2 Autostore mode the CS is pulled on Vcc with a 10k resistor ( always pulled up when the power in on!!! )

in onother datasheet of product similar ( nvram with RTC but not WITHOUT SPI interface) CY14B101KA at page 4 there is the same drow (figure2 autostore mode) but this thime WE is pulled on wcc with 10 k resistor and this provably is the true configuration!!

on another cypress document the application note AN43593 on page 1 the drow FIgure 1 report a autostore configuration equals then CY14B101KA datasheet..!

another question: we use single chip mode : the HOLD pin is pulled on vcc or gnd for work???

please inform me about the error ! we loss a lot of time for redrow our project!!!



 

psr posted on 24 Jun 2011 01:45 AM PST
Cypress Employee
10 Forum Posts

The questions in this posting seem to have been answered through the Cypress tech support channel. I am posting answers here for completion.

Pullup on CS/ pin in SPI nvSRAM:

The Chip Select pin (CS/) should be driven by the controller during normal operation. During power up, it is possible that the controller pin would be floating when it is booting up. In case the controller boot up time is more than the nvSRAM boot up time (tHRECALL = 20ms), if the floating controller output presents a low to the pin, the nvSRAM chip is selected. To ensure that the chip is not selected, it is recommended that the CS/ pin is pulled up. This would avoid any undesired commands due to noise during these conditions.

Pullup on WE/ pin in parallel nvSRAM:

Similar to the above. If the controller pins connected to the WE/ and CE/ pins are floating during power up, and if nvSRAM is booted up, an unintended write can happen if the floating pins present low logic levels at WE/ and CE/ pins. Such an undesired write would corrupt the SRAM location, possibly in the first location (location depends on the levels in the floating address pins). To prevent this situation, a pull up is recommended on WE/ pin.

Pullup on HOLD/ pin in SPI:

HOLD/ pin is active low. Hence a pull up is recommended if this feature is not used in applications, to ensure Hold is not asserted. Even in application where Hold feature is used, it is a best practice to have this pull up in place.



 

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