Hi again folks. In my novice naivete I've led myself to believe that a looping/cyclic chain DMA will issue a "done" flag once it hits the end of the last burst of the last TD. But, this doesn't ever seem to happen...it seems my DMA loops without ever issuing a "done" flag. Is this the correct behavior, or am I missing something? I'd really like to be able to keep tabs on the status of the DMA this way. Thanks all.

I'm afraid that your question already defines the answere: where is the end of a circle?
Since there is no defined end for your td-chain, you might think about to count the DMA-requests to generate a stop-condition.

Bob

Bob: thanks for the answer. I was afraid that would be the case. I thought maybe the transition from the last Td back to TD0 would count as a valid waypoint but I guess not.

The trouble with counting is I can only do that if I use the CPU to manually call the DMA, and I'd really rather not do that. I've been looking for ways around the fanout = 1 and only one on the ADC EOC line in PSoC5 silicon. This is a frustrating limitation...but fortunately, I'm told Cypress is working on new PSoC5 silicon to be released late this year that doesn't suffer this limitation.

You can start two DMAs, your DMA and one dummy started with every EOC transfering a byyte from mem to mem or so. This dummy DMA you can count (with a counter or LUT) and when terminal count is reached an interrupt can be generated. I'd try and it worked.

Bob

One of these days I will learn you cannot post a word based clipboard. Notepad rules

on this site.

If you were dma-ing an address range, source and destination, clearly the last address

constitutes end of chain. That could be detected by flag-on-read of that address,

Verliog solution ?

@PA, I am curious, EOC fanout limitation, would not a simple buffer element fix that ?

Or is this an object description problem in the tool ?

Regards, Dana.

It is not really a fan-out restriction, but the EOC-signal in PSoC 5 may be connected only to DMA or ISR.

Bob

Bob:

Tell me how you would do this with the dummy DMA if I can't connect 2 DMA's on the EOC terminal. I do not want to use an interrupt to call the DMA either. If I chain 2 DMAs end to end, I'm not sure how it would work either: a cyclic first DMA would not trigger the "done" terminal, and a once-through DMA requires the CPU to re-up after every cycle. Again, my goal is to keep the CPU out of this if at all possible.

Dana: How does one check this flag you mentioned without invoking the CPU?

What I am suggesting is that a verilog solution could detect a write or a read

at a specific memory location. Thats an address comparator qualified by a read

strobe. Already the address registers and R/W control logic exist, use Verilog to

buss the data for detection in another piece of HW.

Regards, Dana.

Dana: that sounds like a really good approach. Where can I find the information on the address bus control logic (specifically bus S)? I know there's a TRM for the PSoC 5 registers, but I'm not sure where to look for the other stuff. Thanks for the reply.