Dear Cypress:

I'm using Creator 2.0. I've not yet given 2.1 a try, but if the following are not yet included in 2.1, would you consider adding them someday?

1) JK and/or SR flip flops.

2) JK and/or SR latches

3) The ability to decrement (not just increment) an address (source or destination) with the DMA transaction descriptor.

Yes, I know I can (and eventually probably will) make my own JKs via UDB roll-your-own component. Well, I'm inexperienced, kinda dumb, and really lazy, so I'm hoping one of your fine engineers will just do it for me. :)

SR F-F's of course pretty easy, 2 gates will do it.

J-K, 6 gates, but I agree, if so simple should be in library.

Regards, Dana.

PS : Or I should read the component authoring guide.

Aviator:

This sounds like a perfect project to make your first component and share it with the community. Our fine engineers are working on more complex components to enable you and all PSoC users creating new solutions with new functions all the time without changing your chip.

It's not that our engineers are lazy, they want to provide maximum value to you and the community!

Robert

Yes, Robert, you are right! I just started to watch this video https://secure.cypress.com/?rID=40327 and followed the instructions within Creator 2.1. And lo! I managed to create my very first component. Couldn't stop, so I created some more, have a look at the project

Bob

 Hi Bob

Simple but very usefull modules. Many thanks.

Kamil

@Kamil

To be honest, I did not want to provide the community with new modules, I wanted to point out how easy it is to create own ones. I really started the video, stopped it when something was done and followed it up in Creator ... and so on. It was really a few minutes job to do the first steps until I received something functional. I just can suggest you to give it a try!

Happy creating

Bob

Robert: I never said your engineers are lazy, read what I wrote carefully. It is I who is lazy. Well, lazy but more importantly, rather incompetent. I'd rather get someone else to do it who is sure they haven't created a logic race or implied register (in Verilog).