See generated Verilog ?

	Rocketmagnet posted on 04 Feb 2012 7:23 AM PST Top Contributor 91 Forum Posts

Hi all,

When I place a digital component, and build the project, does that component generate a Verilog file ? Is it possible to see this verilog file ?

Many thanks

Hugo Elias

Re: See generated Verilog ?

	Gautam Das posted on 06 Feb 2012 10:19 PM PST Cypress Employee 742 Forum Posts

Hi Hugo Elias,

You can view the Verilog source file of the UDB based components from the CyComponentLibrary.Lib.

You can access this from your installation folder. In my case, the location turns out to be

C:\Program Files\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib

A word of caution! The C files, Header files and the Verilog files if manipulated here will change forever. The change done, if any, will reflect in the Creator generated files. However, you can view the Verilog file to understand its implementation.

Re: See generated Verilog ?

	srim posted on 06 Feb 2012 10:47 PM PST Cypress Employee 121 Forum Posts

Hello Hugo Elias,

As far as I know, There is also a * .v file generated in codegentemp folder that contains the verilog code generated.

~ srim

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See generated Verilog ?

Re: See generated Verilog ?

Re: See generated Verilog ?