It's cool that the I2C master component supports buffer-at-a-time reads and writes with a Cypress-written builtin ISR. The only feature missing from the API is a function with a signature like:
uint8 MasterWriteReadBuf(uint8 slaveAddress, uint8* wrData, uint8 wrCnt, uint8* rdData, uint8 rdCnt, uint8 mode)
The function would write the bytes from wrData, send a restart, and then read rdCnt bytes into rdData. In other words it would be equivalent to:
status = MasterWriteBuf(slaveAddress, wrData, wrCnt, mode);
// possibly error handling based on status
return MasterReadBuf(slaveAddress, rdData, rdCnt, I2C_MODE_REPEAT_START);
except that it would be handled by the builtin ISR.
Almost all of my I2C interactions are this way: I need to write the "register address" within the device that I am interested in reading, and then read the contents of that register. Performing the transition without having the interrupt handle it is tricky to do without spinning the processor waiting for the initial write transaction to take place at the much-slower-than-bus-clock I2C clock rate. This is a very, very common pattern of use of the I2C bus, almost every I2C device datasheet I know of works this way.
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