Hi,

did you know that PSoC 3/5 has 24 DMA channels with highly sophisticated descriptors? There is an excellent application note that describes how to use DMA with 8- /16- / 32-bit wide peripherals, how to do burst transfers, how to combine the DMA with ADC, DAC, memory to memory transfers and so much more.

See how powerfull components in PSoC 3/5 are

The Application Note is here: http://www.cypress.com/?docID=29495

To support you and complement the Application Note, there is a Video as well.

• http://www.youtube.com/watch?v=D1Gz17bPYm0
  

Finding new ways of doing things that don't even use the CPU provides highly deterministic options for real-time critical systems. Best real-time performance usually does not include a latency of a CPU :-)

Cheers, Robert

Robert,

I actually find the DMA frustrating... especially with use outside of the internal devices and SRAM.

I have programed for decades now and DMA always requires a request and an ack. I don't see anyway in PSOC3 to get an ack from the DMA controller. How am I suppose to figure out when the request is complete?

For example and several people have asked for this. Say we are using a simple high speed AD converter or some other host device. The ADC complete triggers the read of say an IO port to read the sample. BUT... what is going to trigger the ADC for the next sample?

Really we need more info on how to make DMA work out side the box.

The DMA wizard BTW is pretty useless.

Thanks

Gordon

The DMA component has a 'nrq' output, which signals that the DMA transaction is complete. Or do you need something which acknowledges every single transferred byte?

For your ADC example - why don't you use a clock component triggering both the DMA and the ADC? This would allow you a flexible configuration of your timing. You would drive the DMAs drq input by the clock, which is then also the signal to trigger the next ADC conversion.