I'm working on a design where i need to interface to a memory type of device that needs a multiplexed Address/Data bus. i can probably gen up a verilog component to do a version but it would be nice if i can use the EMIF capability built-in to the chip and wrap some more internal logic around it. i think of this a the PSoC way.

i've drilled down a few levels and found some things out about the EMIF component in Creator and its base primitives.

i think i'll need to replace/enhance the cy_psoc3_port_v1_0 primitive verilog generation in the customizer.

can cypress or other experts confirm that something like this is doable? i think i'll need to get the emif port signals out of the DSI and assigned as inputs to some multiplexors and add custom verilog code to generate timing.

i've looked and can't find the documentation for the cy_psoc3_port_v1_0 primitive. where does such exist?

-Ed