AN60305 describes, amongst other things, a "Rail to Rail 9-Bit VDAC with Low Output Impedance", using an IDAC, opamp, and swtiching the polarity of the DAC while creating a waveform. I haven't seen any examples of this, though, and it's not clear to me if this is pracitcal in a manner similar to the WaveDAC component - eg, using DMA with low CPU overhead. Does anyone have any examples of this pattern in use?

Also, the appnote says:

"To ensure the best accuracy, load the proper calibration values when the IDAC direction or range is switched. This can be done with software or DMA."

And the IDAC datasheet says:

"Note When using the ipolarity input to change the IDAC8 polarity, either the Source or Sink mode will no longer be calibrated and could have errors in excess of 25%."

However, I can't find any documentation on how to load calibration values into the IDAC, or on how to determine what values should be loaded.

If you look in tghe TRM and the Register TRM there is a register named DAC[0..3]_TR, but no

info on the relationship of value to the amount it will change a DAC value.

On a broader point, using the sign bit of the IDAC as an extra bit has some serious limitations.

First and foremost, given the trim values themselves are 8 bit, guarenteeing the DAC stays

monotonic over a 512 step range is impossible. Generally speaking thats pretty important in

waveform generation.

One way of doing this would be to feed 0 - 512 to the DAC in production test, and measure

with a precision DVM the voltage, and store a table of corrections. Alternatively do a power

equation curve fit to the data, and use coefficients calculated real time to correct value written

to Vdac for a given requested DAC output. This of course should be over temperature.

The IDAC can be DMAed just like the VDAC, no issue there. IDAC has an advantge, its

settling time ~ 1/10 the VDAC, so higher F generation possible. But once you buffer the

IDAC then settling time slows down. Unless using a fast external OA.

Regrads, Dana.

[quote] If you look in tghe TRM and the Register TRM there is a register named DAC[0..3]_TR, but no info on the relationship of value to the amount it will change a DAC value.

On a broader point, using the sign bit of the IDAC as an extra bit has some serious limitations.

First and foremost, given the trim values themselves are 8 bit, guarenteeing the DAC stays

monotonic over a 512 step range is impossible. Generally speaking thats pretty important in

waveform generation.[/quote]

How is this specifically an issue for using the sign bit, but not for regular DAC operation?

The annoying thing about operating the DAC in only source or sink mode is that you need a reference voltage at one end of the range. If, like me, you're also using a virtual ground, you need two reference voltages in a 2:1 ratio, instead of just the one.

[quote]One way of doing this would be to feed 0 - 512 to the DAC in production test, and measure

with a precision DVM the voltage, and store a table of corrections. Alternatively do a power

equation curve fit to the data, and use coefficients calculated real time to correct value written

to Vdac for a given requested DAC output. This of course should be over temperature.[/quote]

I'd already planned to do offset and gain calibration at runtime. What's not clear to me is how that interacts with the DAC calibration register(s).

[quote]The IDAC can be DMAed just like the VDAC, no issue there. IDAC has an advantge, its

settling time ~ 1/10 the VDAC, so higher F generation possible. But once you buffer the

IDAC then settling time slows down. Unless using a fast external OA.[/quote]

That was the plan. I'm using one of the dedicated opamps as a transimpedance amplifier to do the buffering. DMAing the DAC is easy, but what I was asking about was DMAing the data register, the sign bit, and the calibration registers, which would be a lot more complicated.

"How is this specifically an issue for using the sign bit, but not for regular DAC operation?"

Because changing the DAC from source to sink is a significant circuit topology change, hence

gain error and non linearities are being added on top of the 8 bit part of the circuit design. Eg, more

errors are being added to the exsisting basic 8 bit design.

I also do not know how the DAC cal register is used, I would suggest you file a tech case at -

www.cypress.com

“Support”

“Technical Support”

“Create a MyCase”

Lastly I am not sure DMA would be the sole solution of DAC, DAC cal, and sign changes. Might consider

a verilog approach where the DMA feeds a memory area and verilog handles synching this so data + sign

occur within sample rate of DAC update. Although 2 DMA streams running off same trigger should be able

to do this, depending on sample rate.

Are you fixated on 9 bits for distortion reasons ?  What frequency are you trying to achieve ? I have looked

at WaveDac vs DDS, and there is a place for both, but in general external DDS much higher performance

in terms of resolution, and rate.

Regards, Dana.

 I'm honestly not worried about 9 bits specifically, but I'd like a component that can be referenced to the center of the range (my virtual ground) rather than having to hack around with reference voltages etc.

I'm trying to create quite a clean sine wave, and the DAC for that seems a better choice than DDS, which will require a lot of external components.

But there are already DDS implementations completely inside of the PSoC (e.g. http://www.cypress.com/?rID=39408 or http://www.cypress.com/?app=forum&id=167&rID=66884 ).

You would just need to shift the output level to reference your virtual ground.

Those examples still use the internal DAC, so I'm unclear how they would improve on its resolution or accuracy.

Those examples do not alter DAC resolution or accuracy. Further they are limited in

frequency generated.However for low freq they are excellent examples to use. The

IDAC settling time is ~ 125 nS, and that limits highest freq to 125 nS X samples/cycle

of waveform table. Basically <= 200 Khz solutions, unless you can support a lot of distortion.

And if you have to buffer IDAC to a voltage settling time worse unless you use fast off chip

amp.

External DDS is generally a 1 chip solution + a fast amp (because of  10's to 100's of Mhz operation).

Regards, Dana.

There is another possible way of doing this if you needed much higher

resolution, dynamic range, that is a discrete osc offboard controlled by

a jfet for freq control, and a 16 bit pwm to function as a DAC. But then

you would have high latency to step changes in freq. You could consider

a modified state variable solution, or wien bridge. And PWM is inherently

monotonic as a DAC. Plus you could close the loop by measuring freq based

on xtal timebase to handleT & V changes. Lastly this can be done well into

the Mhz region with PSOC.

One negative is if you need very low freq, DDS approaches shine in this region,

no large charge storage devices needed for oscillator loop.

Regards, Dana.

 I really don't want to use an offboard DAC. I'm happy with the restrictions this places on my maximum sample frequency.

I'll file a case asking about calibration registers. It seems beyond awkward to have to reload these multiple times per waveform, but so is having to have a reference voltage that's at one extreme instead of in the middle.