Hy,

I have a single input signal of 960Hz and i would want to create 2 output signals of 64Hz with a 90° phase shift.

I have a solution if my frequenty would be 3840Hz but,
is there an other way to do this or a way to software wise increase my input frequenty by 4?

//Stop counters
  Counter8_1_Stop();
  Counter8_2_Stop();
//LUT to false, Enable to low, counters are stopped
   RDI0LT1&=0x0F;
//Write to first counter period and comp. value
   Counter8_1_WritePeriod(59);
   Counter8_1_WriteCompareValue(30);
//Write to second counter phase shift value
   Counter8_2_WritePeriod(15);
//Start counters
   Counter8_1_Start();
   Counter8_2_Start();
//Write to second counter period and comp. value
   Counter8_2_WritePeriod(59);
   Counter8_2_WriteCompareValue(30);
//LUT true, Enable to high, counters are started
   RDI0LT1|=0xF0;

Any specific timing requirements between the 960Hz signal and the output?

Would the input change in frequency?

Should the output frequency change if the input changes as well to maintain the ratio? If it is what is the allowable delay between the change of input to the change of output?

What is the tolerance of the duty ration and phase delay of the outputs?

The whole concept is that i'm building an encoder that has A en B signal where B = A+90° or -90°.
The input encoder is 960ppt and the output should be at 64ppt.

So the signal needs to look exactly the same but a time delay between in and out is no problem and the output needs to change with the same ratio if the input changes, PWM is 50% and should be unchanged.

The easiest suggestion I have is to use the PSoC5's PWM which can be adjusted to many needs. If you want a 50% duty cycle use two dividers (FFs) after the 90° shift.

Bob

But how to create a 90° shift with a PWM? When I take the 960Hz as input, I need a period of 15 to get 64Hz output. And 1/4th of that is 3.75 :(

If the average phase shift of 90° would be OK, one could use hardware dithering, but I think this is not what anub intended.

@anub: When I understand you right, you get an input signal (typically 960Hz), which gets converted to an output of 64Hz (via division by 15). Then you need a second output which is phase-shifted (by 90°) to the first output.

Does the output need to follow the duty cycle period of the input (thats what I read from your talk about the 50% PWM)? If yes - how? Each output cycle averages over 15 input cycles, so what should happen when the input varies its duty cycle?

 @hli the duty cycle of the input is 50% and output has to stay 50% this never changes.
Only the frequenty can alter but the inputfrequenty/output frequenty needs to stay the same division by 15.

So i have the same problem as you with the 3.75

 Its basicly this but  with a division of 15 and not 200 like in the example

http://www.psocdeveloper.com/uploads/tx_piapappnote/an2345_01.pdf

My best guess would be to use a PLL to create a signal with higher frequency from your input. You can either use the PLL already existing, by configuring the clock system to feed the PLL from a digital signal. Or you create a PLL on your own (though I'm not sure how easy that will be).

After trying my first suggestion, I saw that the existing PLL needs its clock input in the range og 1 to 48MHz, so you cannot use it :(

Wouldn't something like this give you a start?

Bob

 I was thinking about using PLL, that is why I asked what is allowable delay between changing of input to chaning of output as PLL needs so time to lock and settle.

But if you can get 3840 hz, there are other simple circuit to  meet the other requirments.

 @Bod

Can you explane how your circuit works. Tks

 @bob Well i think i'm just looking at it from the wrong side.
I keep thinking i should multiply my input frequenty by 4 but cant seem find a way how to do this.

@bob this is not guaranteed to work. The data sheet for the edge detector says explicitely that the resulting pule might be shorter than one clock pule. This means the second edge detector might not detect some pulses generated by the first one.

If the rate of change in the inout frequency is not high, and you might allow for a small delay in reacting to changes, you could to the frequency multiplication by measuring the input frequency (or better: get period length of the input signal), and with the result you can configure a NCO to create the desired frequency you need. When you have that higher frequency, you can feed a PWM with it, which is configured to output 2 signals, with a 90 degree phase.

For a NCO, see here: http://www.cypress.com/?rID=39408&cache=0

I also found a fully digital frequency double here: https://www.jstage.jst.go.jp/article/elex/7/6/7_6_416/_pdf

 What is the shape of your 960hz signal, Is it a sine wave or a square wave or a triangular one?

 a square signal

One way to get the 3840hz is to feed the 960hz via BPF and use the filtered sine wave with ananlog mutipler 2 times to get the 4X in frequency. 

Another way is as suggested. Use frequncy counter to count the frequency( or to measure the period). Then generate squarewave 4 times the counted frequency. ( but his may be limited by the accuracy and resolution of the clock of the counter and pulse generator)

I am wondering if it is possible to use a ADC to sample the signal and doing the muliplication digitally.

@Hli,

Yes, I knew about the shortened clock pulses but I took that into account by using a 4 times higher clock rate for the second stage.

Bob

Hilbert transform is one possibility. Here is an ap note for PSOC 1, maybe

port it to DFB in PSOC 3/5 -

www.psocdeveloper.com/docs/appnotes/an-mode/detail/an-pointer/an2328.html

Regards, Dana.

@bob: there is no lower bound on how short the pulses generated by the edge trigger can be. So they might as well be much short than your 250nS the 4MHz clock provides.

@hli

Got it, you're right.

Bob

One solution may be

1. Use a divided by 15 divider with 50% duty cycle output (OPA) . refer to this URL http://www2.fiu.edu/~vjaya002/vlsi%20BOOKS/clock%20dividers.pdf to construct the divider.

2. One high resolution counter (CT1) with 10mhz (or hihger to increase the resolution) clock to count the period of OPA.

3. One timer/counter (CT2) with the terminal count as ¼ of the CT1 reading. The period is updated according to CT2 every cycle. This CT2 is triggered at both the falling and rising edge of OPA.

4. XOR CT2 with OPA to get OPB which is 90% phase shift to OPA.

You may need to add to your software checking of the period,ie too low or too high and also control the output OPA and OPB under those conditions.

This sounds like a good solution, provided the input frequency doesn't change too much (or too fast, because then you might have a lack in changing the reference frequency).