1)What is the delay after which the interrupt starts executing, and also what happens when 2 interrupts of same priority trigger simultaneously?

2) Which is the register which has to be looked for to know the current interrupt which is executing?

3) Interrupts with level trigger- What is the time duration for which the signal level has to be held high to generate two interrupts out of one signal? This is not a requirement but want to know at what time after the first interrupt is triggered second interrupt will trigger.

regards

Akash

1) From TRM -

Case 2 – During the simultaneous occurrence of inter-
rupts:
❐ If INT A has lower priority than INT B, then INT B
wins arbitration and begins to execute.
❐ If INT A has higher priority than INT B, then INT A
wins arbitration and begins to execute.
❐ If INT A and INT B have equal priority, then the inter-
rupt with the lower index number wins arbitration and
begins to execute.

From Cortex Manual -

To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt priority register entry into two fields:

Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler,

If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first.

Regards, Dana.

2) From TRM

Regards, Dana.

3) This might be useful http://www.cypress.com/?docID=41145

and this http://www.arm.com/files/pdf/introToCortex-M3.pdf page 7

Regards, Dana.