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Specific Phase between two WaveDAC Sine Waves
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Specific Phase between two WaveDAC Sine Waves

Mr posted on 27 Jan 2013 2:00 PM PST

1 Forum Post

Hello all,

I need to use a WaveDAC to create a sine wave (audio frequencies) output (know how to do that), and contemporaneously a 2nd one (2nd WaveDAC) which has a (digitally) known / programmable phase delay - from 0 to 360 deg w.r.t the first. Seems like the start of adress incrementing in the table lookup happens at WaveDAC8_Start time - (if the clock is going) which would not create a precise phase difference if used to delay the start of the 2nd. Also - any approach which started the 2nd WaveDAC's clock at a known delay w.r.t the first WaveDAC's clock  could be subject to error over long time (hoping they stay in the known phase relationship - not "re-setting" that relationship every cycle. Any thoughts on a configuration which would re-assert the phase relationship every cycle?

 

Thx




Re: Specific Phase between two WaveDAC Sine Waves

danaaknight posted on 27 Jan 2013 04:26 PM PST
Top Contributor
1773 Forum Posts

You might want to contact Mark Hastings, his email at the end of this

ap note http://www.cypress.com/?docID=41148

 

I suspect the only sure way of doing this is via a verilog based solution, because of

the DMA, even if it is the sole lone highest priority, due to other processes creating

async latency on the PHUB. But Mark is the expert.

 

Regards, Dana.



Re: Specific Phase between two WaveDAC Sine Waves

danaaknight posted on 27 Jan 2013 04:34 PM PST
Top Contributor
1773 Forum Posts

One other thought.

 

Because Creator allows for rapid test bed creation, try a few tests. Look at

basic clock spectrum jitter, then examine the solution you are seeking, looking

at spectral noise noise generated to see how much phase jitter is generated.

 

Regards, Dana.



Re: Specific Phase between two WaveDAC Sine Waves

pavloven posted on 28 Jan 2013 12:19 AM PST
Top Contributor
78 Forum Posts

I've asked a similar question here: http://www.cypress.com/?app=forum&id=2232&rID=72112

Until I do this: the Shift of the phases of the signals I pick up the experimentally.
I've been using this test signal and a logic analyzer.
Add delays and (sometimes to increase the accuracy of) the shift of data in the second(s) table(s)

....................................................
СyDmaChEnable(DMA_Wave_1_Chan, 1);
CyDelayUs(150); //  experiment data
CyDmaChEnable(DMA_Wave_2_Chan, 1);
..................
It seems to me this is enough. I watched at a signals  more than an hour and not noticed the change of phase shift.
There is only a small jitter, but it doesn't bother me.
 






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