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Pure UDB/DP Timer
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Pure UDB/DP Timer

ole posted on 07 Jan 2013 6:18 AM PST
Top Contributor
26 Forum Posts

Hello,

is it possible to write a UDB/DP timer? I need a simple down counter which loads it's count value from hardware register (not written by CPU), which is instanciated in verilog and written from other (DP) stage. At zero count a simple hit signal has to be generated.

The DP has to read this external (parallel in) count value and increment them - using this as A0 DP register, which requires write access to the external one. Following the PSoC TRM this seems not to be possible easy. I can get values from ALU back (parallel out) but this must be written back to the external register connected to parallel in. Is this possible? Which other options do I have.

The goal is to have no CPU/DMA intervention!

Thanks




Re: Pure UDB/DP Timer

hli posted on 07 Jan 2013 12:18 PM PST
Top Contributor
1541 Forum Posts

I think this is possible, though not with the OOB components.

But for a start, you can have a look at the results of the recent component design contest (I cannot find the forum where this happened, but I have the links to the results):

http://www.cypress.com/?app=forum&id=2232&rID=73708

http://www.cypress.com/?app=forum&id=2232&rID=73709

http://www.cypress.com/?app=forum&id=2232&rID=73710

http://www.cypress.com/?app=forum&id=2232&rID=73711

They are all PLD-based, but I think it should be possible to modify them to use A0 as load register.

Also, have a look at the PSoC Sensei blog, which implements a Counter7 (which is native to the UDB):

http://www.cypress.com/?id=2401&StartRow=6&PageNum=2



Re: Pure UDB/DP Timer

ole posted on 08 Jan 2013 12:57 AM PST
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26 Forum Posts

thanks! But, from what I'Ve seen, these implementation

http://www.cypress.com/?app=forum&id=2232&rID=73708
http://www.cypress.com/?app=forum&id=2232&rID=73709
http://www.cypress.com/?app=forum&id=2232&rID=73710
http://www.cypress.com/?app=forum&id=2232&rID=73711

suffer from the limited capabilities of the warp synthese tool to not instanciate DP components and therefore my pterms/UDB are gone ( Note, I haven't tested/checked the synthesis report about resource usage, but from my experience this comes true). This is the problem with my initial top level FSM where 2 counter are required. Writing PSoC components isn't easy like Xilinx/Altera/... FPGA verilog designs due to the limit resources as such and the limited capabilities of warp synthesis.

Anyway, I will have a deep look into the counter7 which may have an DP behind.



Re: Pure UDB/DP Timer

ole posted on 08 Jan 2013 02:39 AM PST
Top Contributor
26 Forum Posts

does the count7 use a DP?



Re: Pure UDB/DP Timer

hli posted on 08 Jan 2013 04:44 AM PST
Top Contributor
1541 Forum Posts

You did not mention how many bits your counter must have - for a small one a PLD-based implementation might be still OK.

Yes, the Counter7-component mentioned is using the DP (actually the DP contains a counter7, the component just exposes it).



Re: Pure UDB/DP Timer

ole posted on 08 Jan 2013 04:55 AM PST
Top Contributor
26 Forum Posts

> You did not mention how many bits your counter must have - for a small one a PLD-based implementation might be still OK.

16bit

> Yes, the Counter7-component mentioned is using the DP (actually the DP contains a counter7, the component just exposes it)

Interesting, since the simu model shows count <= count -1 but it shows the behavior only. Probably there is a low level cy primitive at synthesis?

I need a dynamically reloadable period further more.



Re: Pure UDB/DP Timer

ole posted on 08 Jan 2013 06:49 AM PST
Top Contributor
26 Forum Posts

I did start the design I run into problems to load the A0 from PI using datapath tool.

In the presynthesis behavior model (near line 565) I can read:

 

    // ALU Source A selection
    wire [07:00] pi_internal = pi;
    wire [07:00] sa_internal =  (alu_srcA == `CS_SRCA_A1) ? reg_a1 :
                (alu_srcA == `CS_SRCA_A0) ? reg_a0 : 8'bX;
// THIS PR4 CHANGE WAS FOR BSU_267
    wire [07:00] srcA = ((scr7[`SC_A0_SRC] == `SC_A0_SRC_PIN) |
                ((scr7[`SC_PI_DYN] == `SC_PI_DYN_EN) & fb_enable))
                        ? pi_internal : sa_internal;
    wire [07:00] po   = sa_internal;
 

Following AN82156 Fig.2, Source of PO can be A0, A1 (as we see in the source) and the ALU which I miss here.

Using the DP-Tools I'm unable to set the source to PI, what filed is it. Isn't PI unsupported by the tool? Any recommandations?



Re: Pure UDB/DP Timer

ole posted on 09 Jan 2013 06:11 AM PST
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26 Forum Posts

so far, it seems I'm able to load from PI. Now I have to decrement A1 which doesn't work as expected (only does decrement ones). Is the DP static misconfigured?

 [code]

module timer_v1_0(
                  clock,
                  start,
                  load,
                  count,
                  tc);

   input clock;
   input load;
   input start;
   input [15:0] count;
  
   output tc;

   // general parameter
   localparam ACTIVE = 1'b1;

   // DP/FSM parameter
   reg [1:0]     cs_addr_r;

   localparam DP_RESET   = 2'd0;
   localparam DP_LOAD_PI = 2'd1;
   localparam DP_COUNT   = 2'd2;
   localparam DP_IDLE    = 2'd3;

   always @(/*AS*/load or start) begin
     if (load == ACTIVE) begin
        // load DP/A0 register from PI
        cs_addr_r = DP_LOAD_PI;
     end
     else if (start == ACTIVE) begin
        // decrement A1
        cs_addr_r = DP_COUNT;
     end
     else begin
        cs_addr_r = DP_COUNT;
     end
   end
 

[/code]

 



Re: Pure UDB/DP Timer

rahulram posted on 19 Jan 2013 09:35 AM PST
Cypress Employee
115 Forum Posts

Hi,

Try using the source A rather than SRC B for DEC operation..






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