I am working on a project used for sampling data and transmitting it through I2C; the transmitting portion is working fine, but I am having issues with the SAR ADC. I am sampling at 700KHz, but even when I am attempting to sample a signal at, say, 1KHz, there seems to be a large quantization error. From my calculation, it seems as though it is only operating with 4-bit resolution, even though I have selected 12 bits. The SAR ADC is also configured as Free-Running, with internal clock and single-ended supply input.

I have attached the picture of the sampled signal at 1KHz. I checked the values of data output by the ADC with the de-bugger, and they are the same as those in the figure shown, although the figure shown is after a wireless-transmission, but that is working correctly, so I believe the error to be with the ADC.

Thank you for your help, and if anything else needs to be uploaded, please let me know.

A quick check would be to strip off upper 8 bits, feed to VDAC, and look

at with scope. To eliminate the wireless element. The pic you show is

clearly terrible, 4 bits a good estimate.

Graphing routine getting all the data and have the MIPS to keep up ?

Also maybe post project, or a subset of project, to be examined.

Regards, Dana.

Another quick check, system noise, would be to set up VDAC or an

OpAmp, for output Vdd/2 ~, and look at with scope infinite persistance

to get pk-pk system noise. Do same with SAR input signal.

Regards, Dana.

When you post your complete project here, we all can have a look at to see if everything is ok. To do so:

Build -> Clean Project

File -> Create Workspace Bundle (minimal)

and finally upload the resulting Zip-archive here.

Bob

 Here's (hopefully) the whole project; thank you again for any help you may be able to provide!

 For operation at sample rates above 100kHz the PSoC 5 SAR needs a reference bypass cap on one of the pins, can't look up which one right now, but this should be covered in the component data sheet.  Do you have that cap fitted?  The consequence of not doing do, and then sampling at maximum rate, would be severe conversion errors that might appear as a sort of resolution-limiting quantization behaviour.

Page 6 of SAR datasheet says port0[2] 0.01µF to 10µF bypass capacitor and setting of port to analog high-z.

Bob

Mux settling time also of concern, datasheet shows switching

modes to consider. See attached extraction of speeds.

Regards, Dana.

 The bypass capacitor is wired into the breadboard; could there be any other issues, besides the MUX? At this point, the mux is not being used, so I may try just removing it and seeing if that makes a difference.

You are working with a ref derived from Vdd, so Vdd needs to be quiet. Your

lsb = ~ 1.2 mV. So look at Vdd and Vref bypassed for an indication of how much

noise you will be digitizing.

Some other considerations -

1) You have a R-C settling time associtaed with mux, its C, and A/D input C.

Using standard exponentials you can calc setting time to 1 lsb and see if

its satisifactory.

2) If your are having nosie related problems, consider shutting off as many digital

peripherals as you can while you are doing SAR conversions and mux switching.

Painful but sometimes prudent. Especially any operations switching pins with a lot of

load current, like an LED, or C load.

3) You can always do signal averaging, but that is most effective when noise

is white, not correlated. UP based noise generation tends to be highly correlated.

Food for thought.

Regards, Dana.

Some reference material that may be of use -

a. http://www.analog.com/static/imported-files/application_notes/294542582256114777959693992461771205AN280.pdf
b. http://www.newark.com/pdfs/techarticles/kemet/Replacing-MnO2-with-Conductive-Polymer-in-Tantalum-Capacitors.pdf
c. http://www.analog.com/static/imported-files/application_notes/AN-358.pdf
d. http://www.analog.com/static/imported-files/application_notes/5847948184484445938457260443675626756108420567021238941550065879349464383423509029308534504114752208671024345AN_756_0.pdf
e. http://www.analog.com/static/imported-files/application_notes/77272640AN15.pdf
f. http://www.analog.com/static/imported-files/application_notes/AN-346.pdf
g. http://www.analog.com/static/imported-files/application_notes/AN-1120.pdf
h. http://www.analog.com/static/imported-files/tech_articles/MS-2066.pdf
i. http://www.analog.com/static/imported-files/application_notes/495266810AN-404.pdf
j. http://www.analog.com/library/analogdialogue/archives/43-09/EDch%2012%20pc%20issues.pdf
 

Regards, Dana.

When I build this with Creator 2.1, the bypass capacitor for SAR_1 is assigned to P0[4] (look at the pin assignment table). So you might have the capacitor assigned to the wrong pin. (I think the data sheet is wrong in this regard - the pin is automatically created by the SAR component, there seems no need to create it manually).

In free-running mode, it might be better to use the DMA to get the conversion results - if you are unlucky the next conversion has been started already when you receive the results.

Btw: there is already a conversion method in the SAR ADC component to calculate the voltage: ADC_CountsTo_mVolts().

Hi Faraday55,

The probability of having cross talk between adjacent channels is very high in this case as your SAR ADC is in free running mode.

It is required to stop the conversion before the AMux changes from one channel to the other. If this step is not done, then you might end up getting result of the previous channel for the current conversion.

You have two solution for this:

1) Using Hardware trigger: If you want to trigger the conversion via CPU, then you can connect a control register to the trigger pin and toggle it for every conversion.

2) Using the software trigger to initiate a conversion. This can be achieved by connecting a logical "Low" to the SOC signal and using ADC_SAR_1_StartConvert( ) API to start an ADC conversion. Once the conversion is done, there is no automatic trigger for the next conversion. The user has to explicitly call the API again for the next trigger. This will enable to user to have greater control over the conversion and change the AMux lines only when there is no conversion occurring.

Coming to the connection of the bypass capacitor, the SAR ADC can be forced to use either SAR0 or SAR 1 using the device directive and the appropriate pin can be connected to the capacitor. Else the max sampling rate is limited to 100Ksps rather than 700 Ksps.

One possibility is to select external clock, then use a LUT to supply clock, and

stretch clock on EOC long enough to do the mux change and allow for settling

time. You might file a tech case at

https://secure.cypress.com/myaccount/?id=25&techSupport=1&source=header&CFID=1072952&CFTOKEN=66459405

and state problem and ask how long the clock could be stretched ? Even though it is a SAR

it depends on how its implemented as to whether you can do this.

Regards, Dana.