I'm trying to trigger multiple events at once, but my current implementation isn't building. I'm trying to send a 10 bit signal to activate a bank of 10 digital outputs. To do that, I have 2 control registers (they're limited to 8 outputs) connected to a D Flip Flop. The idea was to send the signal to the control registers, and have the ouput be simultaneous by using the flip flop. Unfortunately, what I have right now doesn't build, due to issues with how I've connected the control registers to the flip flop.

Can anyone help with this? I've attached a picture of what I'm trying to do. Please ask any questions you have for clarification.

Thank you

Your problem is that control register ouputs are all active, and you cannot

directly tie them together.

8 input OR + 2 Input OR feeding a 2 Input OR should do the trick.

Regards, Dana.

 Thank you for the quick response. Any suggestions on how to deal with the width of the terminals? I have the width of the flip flop set to 10, so I tried setting the width of the OR gate to 10 as well. This doesn't work, and neither does leaving them all unconfigured. I've tried a few other configurations, but I don't seem to be getting anywhere.

Thank you

Probably I do not understand exactly what you'd like to do-

Setting 10 pins at the same time from low to high could be done by tying all pins together

Setting a number of pins(max 10) would not need something like an Or-Gate

Only setting the all the pins if ANY of the  control-bits are set would need Or-ing the bits.

Use a 2-stage or, as Dana suggested first stage: one 8-input or and one 2-input or feeding into second stage: one 2-input or.

Bob 

 I want to be able to control which pins are set. For instance. setting just 3 and 8, not necessarily all 10 at once. The pins are tied to a resistor bank, and I want to be able to use multple resistors at once to allow for more resistance options. Do I not need to bother with setting up different widths, and just leave them all at 1? Leaving them all, including the flip flop, at 1 allows the project to build properly, but I'm not sure it will function as I want it to.

Thank you

Or are you looking for something like this?

Bob

 There was an error in that that didn't allow me to see the actual components, but yes, that is essentially what I want. Two control registers go to the input of a flip flop, while a third controls the clock input.

The problem is I cannot connect the outputs of a control register together, so I've put the OR gate network in suggested by Dana. I'm not sure how you got the terminals to tie together in the way you did, I just can't find the option that does that. I think that would still run into the issue that you have one line of width 5 connected to another line of width 10, which has been my primary issue with this. 

If I put everything back to 1 width terminals, it builds, but I'm just not sure that does what I want. If the OR gates and flip flop all have terminals of width 1, do I still send the signal I want to the pins?

Thank you

I may not be clear on what you are doing, but attched will load F-F when

any 1 of 10 goes high, and F-F will remain high for as long as any one

pin is high.

Alternative is output or OR goes to clk of the F-F, anyone pin going high,

FF-F toggles. But if anyone pin stays high no more clking of F-F.

Regards, Dana.

 I want to control which resistors I'm using with the control registers. I don't want them all to be in use at all times. I just need to use the F-F's because the registers are limited to 8 ports, and I need the signal to be simultaneous.

I've resorted to using 1 F-F for each of the 10 pins. It looks a bit messy, but it may work. However, I'm getting an error that the wires have inconsistent base names. It seems to be a problem with the registers, but I'm not sure what the problem is. I've attached another picture so you can see what I'm trying now.

Thank you

To overcome the secret of bus-wiring, have a look at this video http://www.cypress.com/?rID=40097 

The above given example is for Creator 2.1 and builds without error, so what are your problems with that file?

Bob

Do not post pictures, they do help, but they only show a fraction of the project. If you do not mind to have everybody looking at your project, you might upload it to this forum. To do so: Build -> Clean Project

File -> Create Workspace Bundle(minimal)

then upload the resulting .Zip-file here (click on the search button below when posting)

Bob

 I've been using 2.0, I didn't realize 2.1 had been realesed yet. When I tried to open the project you posted, the registers and pins were big boxes with X's in them, I assume acting as place holders for the real components. And thanks, I'll take a look at that video.

This project is for work, and I don't think I should posting the whole project online. I've been using pictures of blank projects, in which I only setup a top design. I didn't think a blank project would be very useful.

There is a possible simplification that would get rid of all the D's.

Control registers have a synch mode that samples all the bits with a clock. Description in

datasheet is -

 SyncMode–Resamples (single-synched) thecontrol bit input from the bus clock to the
selected SC clock before it is driven into the routing.This mode is only supported for PSoC3
Production silicon or later.

A bit confusing, but seems to indicate you can treat the control register as a clocked register

where all ouputs update oin the clock, not the write to the register. Infers its a double buffered

design internally of a flow thru latch.

Try it out, save a lot of flops.

Regards, Dana.

 I tried that first, but I'm using a PSoC 5, which does not allow the sync mode. I believe it only work on PSoC 3.

Thank you

Here's the project for 2.0, but I suggest strongly to upgrade to 2.1 (both are co-existent)

The trick with the busses is: you may edit the properties of a signal by doublclicking on it

Bob

Opps, too fast....

I downloaded Bobs project, and the properties of the control register show

synch mode, and project is PSOC 5.

So maybe you can eliminate the D's.

Regards, Dana.

Yes, Dana is right, but this comes with Creator 2.1 / Control_Reg version 1.70 and will not work with PSoC5 in Creator 2.0, so do not hesitate to upgrade.

Bob

And here is the updated project without FFs for Creator 2.1 (Did you already upgrade?) The thing about is: Although the schematic is smaller and easier to understand the number of macrocells (FFs) is still the same, there are no savings of resources in the PSoC5 chip which is quite understandable.

Bob

Not sure you can draw the conclusion about resources from rpt file.

I ran 4 tests, one empty project compile, one with an 8 bit control register, not synch,

and a project with 8 bit Control reg, no synch, and 8 D's, and last 8 bot control reg with synch

Guess what, rpt file the same for all 4, resources used same for all 3 projects. So looks like

we can't tell for some basic stuff how many resources are used or not used.

Regards, Dana.

@Dana:

Sorry, I do not know what you saw, but an empty project will not use any resources (exept some dedicatet pins) .

That a version with a synced control register uses as much resources as an unsynced with the FFs following does indeed show up that  the generation-step is optimized.

Have a look at the excerpt from the rpt-file of an empty project and the 2.1 version without FFs (sync Control-reg). Sorry for the mis-aligned table but the indentation has got lost.

Bob

Here is what I saw, attached. 4 rpt files pretty much same as test cases.

Could be that D's and simple registers are part of a UDB PLD array, and if entire

UDB does not take a timer/counter/uart then it is not counted as used

in rpt file.

Or there is additional fabric used for simple gates, etc. not shown in RPT

file.

We do know a synch Control register has to be double buffered, hence

use 2 sets of flops on each bit, vs 1/bit for a simple register.

Conclusion is that we would not be able to tell if synch Control reg uses

more fabric not already dedicated to it, or if it needs less gates when

configed as synch. Eg. the efficiency associated with a specific design

vs cobbling together 2 designs, control reg + synch reg (the D's), Only

way to tell this would be contact designer, or get a better RPT report,.

Regards, Dana.

Dana, there IS something wrong with your .rpt-file.

If you use a control-register it will be shown in the number of used control-registers.

Your design doesn't use any pin-component. Are you really sure that the optimizer left something from your schematic? I'm sure that "Unused parts of your design have been optimized-out".

Better connect your design to a handfull (or 3 bit more = 8) pins and let it build again...

Bob

 Wow, you guys were busy over the weekend. I upgraded after you told me 2.1 was out. I just wasn't aware it had been released yet, I thought it was still in the beta program.

I just tried building and programming with the registers in sync mode, and it worked! My F-F schematic also built properly, but i like being able to use sync mode much more. As far resource use goes, it's not something I'm worried about yet. While this is a bigger project than I've ever undertaken, it doesn't seem big enough to overuse the PSoC.

Thank you both for helping me with this, it's very much appreciated,

Matt

I concur Bob, no savings in hardware, but -

1) I personally saved a lot of erasers.

2) Save 1e-23 trees, eg paper usage when printing schematic.

3) Saved electricity, less printing

4) Saved toner, less printing

5) Saved time, less drawing time, more time to eat junk food

6) Subtracted from the US GDP, more time to grow the countries DEBT with foolish expenditures and

excessive medical costs due to junk food consumption

7) Saved power, less energy

Etc. so forth.

So Bob, looks like a win to me :)

Regards, Dana.

@Dana

What's about an invitation? And then we are going to guzzle all that saved stuff away!! Do not forget to invite the optimizer!

Bob

Matt, you are always welcome!

Dana's posts are shaped by a project he has got which is at the very brink of using just a bit more resources than the chip provides (Here I would normally put some smileys, but this &!"%§ing forum software still crashes when I try). That's the reason why we like have a look at the resource usage and at the performance of the Creator software.

May you never run out of resources
Bob