in the following snippet of a FSM, which drives the DP, I've get the error

Synchronous and asynchronous events cannot be mixed in a timing control.

   always @(posedge clock or /*AS*/next_state or reset) begin
      if (reset) begin
         state <= STATE_RESET;
      end
      else begin
         state <= next_state;
      end
   end
 

How are they handled correctly, the resets. I've found nothing in '"Best Practises' about this.

Hi,

if you look at the error message you get a strong hint.

"in the following snippet of a FSM, which drives the DP, I've get the error
Synchronous and asynchronous events cannot be mixed in a timing control."
 

Reset is an asynchronous event, it happens when it happens, not waiting for a clock while the other events are synchronous to a clock.

Don't mix them.

thanks!

Folowing the presynth simulation implementation of DP it's synchronuous!♠ So it shall be:

 always @(posedge clk or posedge reset)

But how to handle sensity list of next_state, required by modelsim? Using `ifdef etc?