JJWarriner posted on 07 Jan 2013 01:09 PM PST
4 Forum Posts
I know them by heart.
I think I may have figured it out actually. I found an app note that was partially helpful: EP58353.
So a brief explaination of the crucial details:
I have the following registers settings on the DFB (This was the tricky part for me):
Filter_COHER_REG = 0x55;
Filter_DALIGN_REG = 0x0F;
I have two DMA's, one to transfer from ADC to DFB, and on to transfer from DFB to SRAM. Here are the configs and addresses from the two.
ADC to Filter:
CyDmaTdSetConfiguration(DMA_DelSig_TD, 2, DMA_DelSig_TD,0);
CyDmaTdSetAddress(DMA_DelSig_TD, LO16((uint32)ADC_DelSig_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEA_PTR));
Filter to SRAM:
CyDmaTdSetConfiguration(DMA_Filter_TD, 2, DMA_Filter_TD,TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_Filter_TD, LO16((uint32)Filter_HOLDA_PTR), LO16((uint32)Filter_Output));
Like I said, it appears to be working now. I'll need to spend some more time with it to be sure.
I'm a little concerned about the output of the ADC being in 2's complement form and the DFB not handling that. I have to check to see what the Filter puts out when a negative value comes from the ADC.
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