I am using the ADC_SAR in my project and cannot get it to produce samples at the conversion rate that I've set in it. I have set the ADC to run at 1MSPS (the maximum). I have also set the Master Clock in the system wide resources at 72MHZ. However with this setting I am getting samples at around 133kSPS. My ADC resolution is set to 10. I read my ADC register in software as shown below. Is there some setting that I'm missing here?

        for(j=0;j<numOfSamples;j++)
        {
            /* Wait for end of conversion */
            ADC_SAR_1_IsEndConversion(ADC_SAR_1_WAIT_FOR_RESULT);
            voltageRawCount[j] = ADC_SAR_1_GetResult16(); /* Get converted result and store in array voltageRawCount[ ]  */
        }

Hi Kema,

1)  If you are using ADC which is sampling at 1Msps, then it is advisable to use DMA to do the transfer of converted value from ADC to a specified location.

Using CPU to transfer the converted value will be a time consuming process.

You were getting the value at 133Ksps because you were limited by the speed of execution of the instructions by CPU.

Using DMA to do the data transfer with the EOC of the ADC connected to the DRQ of DMA will make it hardware controlled without the intervention of CPU.

2) Limit the Speed of Master clock to a max of 66MHz. It should be sufficient.

Thanks a lot Dasg, but can i also ask another question just to fully understand things here (i'm a newbie). You say I should use 66MHz for the master clock - why? Is there some calculation you use to arrive at this value? I havent yet quite grasped the relationships in the clocks yet. Thanks again!

Hi Kema,

In PSoC5, the IMO and PLL together can generate upto max of 67MHz Clock. Hence, I suggested the use of 66MHz Master Clock.

If you are planning to use derived clocks in your schematic, then you can get a good accuracy by choosing the master clock which is a multiple of that frequency.

Example, if you are using a 16MHz clock in your design, then setting the master clock to 64MHz will yield a more accurate clock than using a 66MHz or 67MHz Master clock.

The use of SAR ADC with DMA is illustrated in the code example which is available at the following link.

Hi Gautam,

I have a related question about the SAR ADC sampling rate. Some app notes claim hat the sampling rate is up to 1Msps. But the configuration menu on PSoC Creator and the PSoC5 datasheet state 700ksps only (631.6ksps actually in Creator). The SAR ADC uses internal clock of 12MHz by default. Do you mean we can get close to 1Msps by using external clock of 66MHz? But won't the higher frequency reduce the effective bit resolution?

Thanks, 

Eric

Please do not post on a thread which is 1.5 years old. Please open a new one, this will increase your chance of getting a good answer.

To your question: the PSoC5 SAR ADC is limited to 700ksps, as its silicon cannot yield better performance. The PSoC5LP can handle 1Msps. This is also stated in the data sheets. (On the PSoC5 the SAR ADC needs 1 clock cylce more per conversion, and can handle only a lower clock).