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Ah, OK, now I've read AN61290, and of course it is much clearer. Thanks so much for that reference, it's really handy. Maybe Cypress could include this in the "related documents" for the PSoC 3/5 product pages? That would help other designers too.
For anyone who's interested, here are the details for "2 pin" debugging with SWD.
First and foremost, SWD debugging is at least a 4-pin debugging option, NOT 2 pin. This is not at all clear from the CY8C55 Family Datasheet, the PSoC 3/5 Architecture TRM, nor the supplied documentation with the kit, all of which only discusses SWDIO and SWDCK. XRES and VTarget are only mentioned in reference to JTAG.
Perhaps this could be corrected or updated in future revisions?
So, SWD debugging requires the following connections in order to work :
- SWDIO
- SWDCK
- XRES
- VTarget; and, of course,
- GND
Optionally, SWV may also be required.
I guess for me the choice is to use JTAG and have the ability to perform boundary scans, or SWD and not worry about boundary scanning.
I'll take the risk and go with the non-boundary-scan option, if only because it means less re-routing!
FWIW, the processor I replaced (eZ80F91) truly required only two signals, TCK and TDI, along with ground of course. I guess that's why I was confused by Cypress' reference to two-pin debugging - I assumed they meant two pins like Zilog meant two pins! Ah well, I learn something new every day!
I hope this helps others who may be in the same boat!
Cheers (and thanks again for the great support)
PCPete
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