So I read the application note regard peak detection on the PSoC (AN60321) and the Peak and Hold method is exactly what I am looking for, only problem is I can't get it to work at a frequency faster then 4 MHz which it says is due to the mixer being used (The LO cannot exceed 4 MHz). I am trying to measure the peak voltage of a pulse that is about 3 microseconds in duration so I get about 12 samples per pulse (3 microseconds/250 nanoseconds).

Is there any way to get around the 4 MHz macimum LO, or is there an altogether better way to detect peaks at higher frequencies?

What is the latency you are seeking, is it the 12 sample width ?

You can always do a peak detector with fast external OpAmps (2) and fast diodes.

Or use PSOC VDAC and Comparator, its has 110 nS response time at high power,

and use a binary search algorithim on the VDAC (which feeds one side of the comparator)

to determine peak via comparator trip relative to VDAC setting. If comparator not fast enough

use an external comparator, fast ones are cheap.

Regards, Dana.

One consideration I forgot to mention, VDAC settling time ~ 3 uS, whereas IDAC ~ 200 nS.

Note VDAC settling speced to .1%, but its only 8 bits, so Ts < 3 uS for 8 bits, 1 LSB.

So in short you could use IDAC to feed your comparator as it is not presenting any significant load.

Regards, Dana.

Well, thinking bigger picture here I need a system that I can adapt to also do a peak detection on pulses that are about 5 nanoseconds in duration. Also these pulses may or may not be periodic depending on the source. It is not important that I detect every pulse, however I need to detect enough so that I don't loose any information such as a change in the peak of a pulse.

I was thinking that I could maybe stretch my pulses so that they are in the milliseconds.

The end goal is to see how capable the PSoC is so if it can be done on the PSoC I need to figure it out using very few to no external components.

Dana, if I understand your VDAC+Comparator method I should increase the VDAC output into the comparator until the comparator changes, signaling that my VDAC output is now larger than my analog input. I think take my previous VDAC value and somewhere in between those two values is my peak?

Here is an appnote http://www.cypress.com/?rID=41001 concerning peak-detection.

Bob

Bob, that is the app note I mentioned in my original post, and as I said earlier none of those methods are fast enough for my needs.

Dana, what instead of "increasing the VDAC value" I ment something along the lines of your binary search. That is increase the value check the comparator output, either increase it again or decrease it by a smaller amount depending on that value. Is that more correct?

The VDAC comparator method. Assume Vref = Vdd/2.

You start algorithim at VDAC = Vdd/2, check output (cout), if ccout is false then VDAC

is < Vpeak, then output VDAC = 3/4 Vdd, check cout again. If false, output 7/8 Vdd

to VDAC, if true output 5/8 Vdd. You keep halfing the increment applied to VDAC

up or down until it converges. Makes for a fast sort. Its a form of the bublle up bubble

down search algorithim. www.codecodex.com/wiki/Bubble_sort

Yiou mentioned earlier 5 nS in the post, I assume thats 5 uS....

Regards, Dana.

Ooops, I overlooked the AN-link. Sorry

Bob

No, it wasn't a typo I ment 5 nanoseconds but I'm not sure if the PSoC is gonna be capable of that sort of speed unless I can stretch the pulse out.

I'm currently trying Dana's method with the IDAC, I'll let you guys know how it goes.

The approach I suggested is still challeneged at the uS area, I think it would

require a little ASM. That being said its shifts and adds, no heavy math.

5 nS peak detection, one approach, lots of latency, is to do equivalent time sampling reconstruction.

Like used in scopes with low sample rates but high analog bandwidth. This ap note explains some

of it.

http://www.tek.com/application-note/real-time-versus-equivalent-time-sampling

http://www.co-bw.com/EE__Oscilloscopes/XYXZs_of_Oscilloscopes_Index.pdf

Regards, Dana.

http://www.edn.com/design/analog/4347624/High-speed-peak-detector-uses-ECL-comparator

Regards, Dana.

So this is the code I am using:

currIDAC = IDAC_MAX / 2;
    IDAC8_SetValue(currIDAC);
   
    while(1){
            update = 0;
            prevFlag = compFlag;
            compFlag = Status_Reg_Read();
           
            //If threshold is less than the peak
            prevIDAC = currIDAC;
           
            if(compFlag == 1){
                delta *= 2;
                currIDAC += IDAC_MAX/delta;
            }
            else if(compFlag == 0){
                delta *= 2;
                currIDAC -= IDAC_MAX/delta;
            }
            currIDAC += delta;
            IDAC8_SetValue(currIDAC);
           
        LCD_Position(1,0);
        LCD_PrintNumber(currIDAC);
    }

I can see the IDAC increase and decreas as it should, but it doesn't line up with the pulses.

The IDAC increases for about 3.5 uS until it flatlines at its maximum value where it stays for about 450 uS then it decreases for about 4 uS stays low for about 180 uS then repeats

All I get on the output is either 0 or 255

I tried to have a seperate comparator with a fixed threshold that would output high when a pulse was detected and I tried using this as a trigger to update the value of the IDAC based on the value read from the IDAC's comparator but this had no effect.

Here is the project if it helps

Your code does not look right.

First question, do you have a terminating R on IDAC output ?

Next question is what is amp of input waveform ? You have to scale IDAC and pulse
signal path such that they match at max Vpulse, to maximize dynamic range and
resolution of the solution.

Just in case compiler not "aware" use >> and << vs multiplies/divides.

Lets assume the following

IDAC 0 - 2.04 mA
IDAC R = 600 ohms, therefore full scale = .6 x 2.04 = 1.224 V max pulse amplitude

We start at 1.02 mA = 0x80, 128 dec, half scale, .612 V

Pulse amp is 1.0 V

So first trial is

1) VDAC = .612
2) comp = low, the pulse is higher
3) So we add last VDAC value + 1/4 VDAC range = .612 + .306 = .918
4) comp = low, the pulse is higher
5) So we add last VDAC value + 1/8 VDAC range = .918 + ( 1.224 / 8 ) = .918 + .153 = 1.071

6) comp = high, VDAC > pulse

We know know 1.071 > Vpulse > .918, but we have more resolution than that. Our resolution
is 1.224 / 256 = 4.78125 mV

7) So we take VDAC value at beginning of last test, and add 1/16 to it
8) comp = .918 + ( 1.224 / 16 ) = .9945
9) comp = low, vpulse > .9945
..
..
..
..
Work out the same scenario when comp indicates pulse is lower, another switch flag. Its
all part of the same routine. You end when you want to divide (shift) by 512 (9 bits), as
the DAC is only 256 (bits).

Note some numbers are not precise above, I got lazy just using a calc, not integer math.

Regards, Dana.

I missed your project post, just looked at it. Some questions/observations -

1) Looks like IDAC is not terminated in 600 ohms, it outputs I, but comparator needs V. So

terminate it.

2) Cascade of PGAs, I assume what you are doing is level shifting the pulse to be in the CM range of

the comparator ? Here is a technique, attached excle file will help calculate R's needed -

http://electronicdesign.com/article/analog-and-mixed-signal/use-excel-to-calculate-a-d-level-shifter-resistor-.aspx

Regards, Dana.

Cascading PGAs.

You have to be careful here as phase margin of a cascade can get you into trouble.

The PGAs are fairly well characterized, but no spice models to verify what you are

doing is OK. Additionally stray C can play havoc with a cascade, even a non cascade.

There are Scope techniques in the time domain that can look at phase margin, if you do not

have a network analyzer. Google this. Just simply looking at step response on a scope, ringing,

that is severly under-damped, will give you an indicatrion device to device will cause you problems

in the design.

Regards, Dana.

Essentially what you are building is a SAR ADC, the algorithm to run it.

Page 11 shows algorithim -

Sure enough here is a solution in PSOC 3 for a SAR with LUT and SR.

http://www.eetindia.co.in/STATIC/PDF/201006/EEIOL_2010JUN16_SIG_AN_01.pdf?SOURCES=DOWNLOAD

Regards, Dana.

If I go back to your earlier post -

"Well, thinking bigger picture here I need a system that I can adapt to also do a peak detection on
pulses that are about 5 nanoseconds in duration. Also these pulses may or may not be periodic depending
on the source. It is not important that I detect every pulse, however I need to detect enough so that I
don't loose any information such as a change in the peak of a pulse. I was thinking that I could maybe
stretch my pulses so that they are in the milliseconds."

None of the methods suggested, even the equivalent time sampling used in high performance scopes, can
be used due to the aperiodic nature of your signal.

Its brute force time. ECL/GAS due to 5 nS requirement, and a much faster SAR/sampling/OpAmp speed

approach for the 3 uS kind of pulse. Unless you compromise some of the requirements. Pulse stretching

is a possibility, but then you miss a lot of pulses for the 5 nS case.

Regards, Dana.

Could this help? 

http://www.edn.com/design/analog/4347624/High-speed-peak-detector-uses-ECL-comparator

Cheers :-)

I did already have resistors at the output of my IDAC, my maximum pulse height after the PGAs is about 1.4 volts so I set the resistors so that they would make just over that. I have about 6.5k ohms at the output and with a maxe IDAC output of 255 uA that gets me a maximum voltage of 1.6575 V.

Dana, it seems as though in your walkthrough explanation that you put the comparator on the non-inverting terminal of the comparator such that it outputs high when the IDAC output is higher than the pulse output. Is there any advantage to doing it this way as opposed to the comparator output being high when the IDAC is lower than the pulse?

Also, using the SAR ADC mentioned I run into that same problem as earlier where the sample and hold doesn't run fast enough to capture the data points I need, and as the signal is aperiodic I can't set up the interval to just get sequential samples from different pulses (I can't find the link explaining that at the moment) but as far as I know I can't use the SAR method due to that sample and hold.

I may be able to relax my needs and settle for something that doesn't catch every pulse, so if there is someway I can capture a signal 5 uS pulse and then completely digitze it with enough resolution to find the peak that would be enough.

The comparator inputs can be swapped, logically you just modify routine to accomidate change of sign.

Another consideration, PGA slew rate, which affects pulse response, is < 1 V/uS, keep that in mind. You

are affecting settling time to get at the pulse amplitude. Ie. PGA SR its a bit marginal.

Lastly its the aperiodic nature of the signal that is the biggest stumbling block regarding the 5 uS

type of pulse. Thats why we use scopes with 100/200 Mhz BW, but have 1 Ghz or better samplers

in them, to capture faithfully short duration one off pulses.

Another alternative is use comp to control a S/H, such that if S/H's value is below pulse comp initiates

a S/H acquire. The comp is fast enough, the S/H slew rate/acquisition OK at 1 uS for a 5.5 V step.

Then you periodically measure the S/H output, and reset S/H with a mux change to select ground as its

input. The S/H would examine every pulse, until you stopped comp update and measured and reset it.

The delsig will perform 384,000 SPS at 8 bits. Thats 2.6 uS. So maybe you would not miss too many pulses

with this approach.

Just a thought.

Regards, Dana.

I had previously looked at the Del Sig, but a sample every 2.6uS would only get me 1, maybe 2 samples per pulse which can hardly be considered a measurement.

Couldn't I do a sample and hold and save that value if it is higher than threshold A which determines if what is being seen is a pulse, then continue doing sample and holds and replacing the saved value with any held value that is larger than it. Although it may not be accurate and it could take some time to actually get the peak, I think it should let me get the peak as well as still be able to count my number of pulse occurances should I want to.

Dana, I'm a little confused by your S/H method you mentioned, could you go a little more indepth?

Something like this, attached.

Regards, Dana.

So the way this works -

1) Mux feeds Vdd/2 into S/H.

2) Comparator, if it sees pulse is > S/H, forces S/H to sample, until
S/H output exceeds pulse amp + the hysteresis, then comp forces S/H
back to hold mode.

3) You initiate an A/D conversion.

4) You switch mux to other reference, which is ground, and reset the S/H.

I left out a little logic so that when you do this step you force S/H to sample
indepentant of what the comparator is doing. AND/NAND to force S/H into sample.

5) You switch mux back to Vdd/2, go back to step 1).

It might be psosible to automate this all with a LUT, try it.

Regards, Dana.

Something like this should work for the logic right?: (attach)

Basically I OR the output of the comparator with a control register bit that I can set to high when I need to reset the S/H

When that control register is high it should override anything coming out of the comparator.

Hmmm, nevermind that last post that logic won't work. I need to have a way so that when the S/H output is back to 0 it reinitiates the whole sequence.

The only thing I do not like about the approach is need to run A/D in continuous mode

in order to get high conversion rate. If you do single conversion SPS drops by ~ 3/4 to

~ 91,000 SPS.

Continuous mode means you could be converting while S/H is updating.  Not good.

More challenges.

Regards, Dana.

Does the Start_Convert() and Stop_Convert() not affect the ADC when its in continuous mode?

Also is the speed of the ADC important at that point? Once I need it to convert I'm no longer looking for the peak as it has been found using the S/H + Comparator. Of course this only finds a value close to the peak (hopefully) but Once my comparator has dropped to low I then just need to convert what ever value made it do so.

The sample and hold should be reset after just 1 sample from the ground reference correct?

From datasheet looks like these functions do work in continuous mode. But makes

me wonder what effect on SPS that has in continuous mode. Eg. does it add any more

latency beyond the time between stop and start ?

voidADC_StartConvert(void)

Description: ForcestheADCtoinitiateaconversion. If inSingleSamplemode,oneconversionis
performedthentheADChalts.If inoneof theotherthreeconversionmodes,theADCruns
continuously.

If theADC_StartConvert()functioniscalledwhiletheconversionisinprogress,thenext
conversionstart isqueuedandanewconversionwill startafterfinishingthecurrent
conversion.If youwant tostartanewconversionwithout waitingforthecurrentconversionto
finish,thenstopthecurrent conversionbycallingADC_StopConvert().Afterstoppingthe
conversion,restarttheconversionbycallingADC_StartConvert().

Parameters: None
ReturnValue: None
SideEffects: None

voidADC_StopConvert(void)

Description: ForcestheADCtostopall conversions.If theADCisinthemiddleof aconversion,theADC
will bereset andnot providearesultforthat partial conversion.

Parameters: None
ReturnValue: None
SideEffects: None

Yes, S/H has to be reset after each measurement.

Regards, Dana.

Why doesn't the S/H here just always capture and hold the same value, that is why is its output not always Vdda/2?

What about something along the lines of what is in the imaged attached?

In this I'll S/H the amplfied pulse and compare it with another S/H

If the comparator is high, the 1st hold value is larger than the second, then the second S/H will take on the value of the first

In this way I'm storing my max value in the 2nd S/H and when I find something larger I replace it.

I guess the down side to this method is that it would take several pulses to actually be able to determine a peak.

...image...

Vdd/2 is nothing more than a forcing function. After a reset, the comparator

tells the S/H to sample, until it reaches the pulse amplitude. So the S/H slews

to the pulse peak, forced by Vdd/2. Vdd/2 is arbitrary, it should be >>

Vpulsemaxever.

I am fooling around using a T/H vs a S/H, eliminates some logic. My design

still crippled, appears to be capturing the - peak of the waveform. My head

is spinning :)

Regards, Dana.

I appreciate you taking your time to help me Danna, I feel like we have come a long way since I first posted.

I have managed to get something that works fairly well, but I believe it will only work well with periodic signals. It's basically just a comparator with a VDAC as its inverting input and the signal as its non-inverting input. I then start the VDAC out at 255 (4.080V) then sweep it down until my comparator output goes high, then I sweep up till the output goes low, etc. This has allowed my to capture the peaks of my signal through a generator even while I increase/decrease the amplitude on the run. However, I don't believe this method will be sufficient if I have aperiodic pulses with varying amplitudes.

Another though is that it seems as though the pulses I will be receiving are pretty consistent in shape, that is if I can determine the width of the pulse I should be able to say that at 10% of its width these pulses generally peak. Although its a stretch this method might work as long as I can justify those assumptions.

As far as using the S/H and T/H is there any way to on pulse 1 hold a value at t = 0 then for pulse 2 hold a value at t=1. and so on. I think this would require having a threshold set to detect when the pulse actually starts, then some amount of delay, then a S/H. What do you think about that?

If I were to do PW I amp the crap out of the incoming signal and feed to

a comparator to give me edges, then just use a free running counter

or timer to measure edge to edge width. You would not need S/H or T/H.

However, if I wanted to measure width at a given threshold I would just use

the comparator with two isr attached to it, one for + edge, one for negative.

Still have a fre running counter, its size / clock set to handle max width, its

resolution then becomes clock / 2ⁿ. ISR just reads counter value, and subtract

previous value. Note you have to handle counter rollover issue when doing the

 math. Or restart counter at full value, and be sure width sufficient from every

allowing it to roll over.

Regards, Dana.

So I took one of my previous methods and changed the sweep to a binary sweep as you mentioned earlier and I can find the peak a lot faster even at low pulse counts. Attached is the top design, and it is pretty simple. Basically after I do the amplification I then send the signal through 2 comparators. One of them does simple pulse detection, this is used more so at low count rates so that I only change the VDAC when I get a pulse. The next comparator is then what actually determines if I find the peak or not. I sweep through the VDAC range using the following code:

if(detection == 1){
            VDAC_val[1] = VDAC_val[0];    //Save the VDAC value so we can compare against it later
            detection = 0;
           
            if(delta == 256){
                peak = VDAC_val[1];
                delta = 2;
            }
            //If the VDAC value is less than the input signal
            if(compFlag == 1){
           
                //If there was a rising edge at the comparator output
                if(was0 == 1){
                    delta = delta<<1;    //Multiply delta by 2^1
                }
                was0 = 0;
                was1 = 1;
                VDAC_val[0] = VDAC_val[1] + VDAC_MAX/delta;
                VDAC8_SetValue(VDAC_val[0]);
                compFlag = 0;
               
                if(VDAC_val[0] == VDAC_MAX)
                    VDAC_val[0] = VDAC_MIN;
            }
           
            //If the VDAC value is greater then the input signal
            else{
           
                //If there was a falling edge at the comparator output
                if(was1 == 1){
                    delta = delta<<1;
                }
                was0 = 1;
                was1 = 0;
           
                VDAC_val[0] = VDAC_val[1] - VDAC_MAX/delta;
                VDAC8_SetValue(VDAC_val[0]);
                if(VDAC_val[0] == VDAC_MIN)
                    VDAC_val[0] = VDAC_MAX;   
            }
           
            //Print the VDAC value whenever it is updated
            LCD_Position(0,0);
            LCD_PrintInt8(VDAC_val[0]);
           
            LCD_Position(0,5);
            LCD_PrintNumber(delta);
           
        }

I may change it so that instead of the sweep starting over, it increases by 1 then decreases by 1 so that it floats around the peak value. Then if while it is doing that the comparator output stops changing I know my peak has changed and I should start over.

Any recommendations on this so far?

Shoot me the project archive, I would love to look at it.

I have a design working and looks like it skips very few pulses, but I am at a remote site

with a low performance scope. I need my 2 Ghz scope (sampler) to get a real idea

if it is working. I find this an interesting problem, in light of the fact we are dealing with

relatively low f signals.

Regards, Dana.

KK I am actually in the process of making a trough detection as well using the same method. Currently my pulses have about a 1V DC offset even after they come out of a large DC blocking cap o.O but this offset decreases with a higher count rate (due to pulses riding on the tails of their predecessors) so I am trying to eliminate that so I can get a striaight out amplitude of my original input pulse. Once I get that sorted out I'll post my project.

So I am having a hard time with the trough detection and I may just drop it altogether =/

You would think it would be the same as the peak detection except when doing the binary search stuff.

Where you would add to find the peak you should subtract to find the trough and visa versa, or so I though. Not having much luck with it actually doing that though.

Anyways this code should still find the peak and once it can it oscillates around the peak +-  until the signal goes out of that range. So far it detects the peak of 3.5 uS pulses that are coming in at a rate of 66 pps however it takes a while to find the pulse as it only updates the VDAC whenever a pulse is detected. Otherwise the VDAC will center around the baseline of the signal.

 in the project what is the input to pin 2