Hi, I am trying to drive an N-Channel MOSFET (SI2302ADS-TI  http://www.mouser.com/ProductDetail/Vishay-Siliconi/SI2302ADS-T1-E3/?qs=jcx%252b0HVgj2b5KfVm3X6q9lulTMzrSQ1bbldi99EzJiE%3d)

I have a PSoC 3 hooked up in the following way:

Powered via USB, set to 5V outputs (I know that this is not recommened as the 5V is unreliable here But I get about 4.8V)

P1[6], P1[4], P2[6], and P2[4] are my four digital outputs.

I read that:

"iØ  “it is possible to increase drive power by connecting multiple GPIO pins. In this case, the levels written to these pins must be the same. Use low value series resistors on each pin so that proper current sharing between the pins takes place.” (http://www.cypress.com/?id=4&rID=28549)

So I have put 100 Ohm resistors after my output.

The problem I am haivng is that I cannot drive the MOSFET with any number of pins.

I am almost positive that it is a problem with me not being able to drive the MOSFET completely but I'm not sure what more I can do.

Any advice?

In your case you are driving a high Z gate, so no DC current is being used

other than leakage. So you do not need R's for current sharing, you basically

want all the current you can get to drive the large Cgd of the MOSFET.

The other issue you have is how fast are you trying to drive the MOSFET,

clock rate ? Driving a 300 pF load, your rise time will be the limiting item

for speed. CMOS outputs generally sink a lot better than they source.

If you are trying to drive at fast clock rates consider a driver or an NPN/PNP

discrete driver solution.

What is the actual load you are trying to drive ?

Regards, Dana.

Currently I have an external timing circuit that is high for 10u seconds and off for 1u seconds so a frequency of about 90k Hz.

The MOSFET is being used to drive a power MOSFET that the PSoC couldn't drive by itself (http://www.alldatasheet.com/datasheet-pdf/pdf/155699/MOTOROLA/MTD2N50.html).

This MOSFET is then the driving force of a boost converter that takes 9V to 500V.

Here is a quick schematic:

The Comparator and both NOT gates are done inside the PSoC

Hope this is useful

Also, how much current can be sourced out of GPIO pins? I read at the knowledge base here that it was no morre than 10mA, and in creator 2.0 under the output tab for a digital output pin it says it will source 4mA.

Then I should be able to find a turn on time by taking my gate charge Qg and dividing by my gate current Ig

I then need to add the turn on delay time and rise time to get a final value?

I can run the Power MOSFET directly with the PSoC 3 using a different method, one that includes using a comparator that controls the output of a PWM block. This PWM sends out a single pulse each time the comparator is checked and has a high value. This pulse is 75u seconds long which gives it a frequency of 13.33K which is much slower. Could that be my problem, that my NOT gate configuration is switching too quickly?

If you look at datasheet there is a guarenteed section with up to a Vddio of 3.3, and then

a set of typical curves that show Voh and available current vs Vddio. So 5V operation means

you have to interprolate. Very involved but I think it could be determined by using defining eqautions

for a MOSFET with bulk effect by writing the equations for both Voh and Vol and eliminating unknown

variables. Painful.

The Turn on and Turnoff delay is done with a generator and a known source resistance. In short

you do not have to include additively, but you do have to spice model the PSOC case, and unfor-

tunately Cypress has no GPIO models I believe. So you would have to wing it with a choosen fudge

factor. Keep in mind PSOC case source current drops as Voh rises to Vddio.

Your comment on effective pulse witdh for drive, absolutely, if Tpw is too low that would not give enough

time for MOSFET to turn on.

Regards, Dana.

Ok, so I guess what I don't understand is why when I send my output over 4 pins and hook them all up to my circuit I don't see 4 times the current. I would see a slight rise in the voltage when I measured over a 1 ohm 3W resistor as I added pins, but nothing substantial. Is there something I am missing with this?

Is the 1 ohm the load of the MOSFET being driven ? Or a current sampling

R in series with the gate drive ? A complete schematic might help.

Also look at gate drive with a scope, does it meet the necessary level to

get low Rdson at your switching freq ?

Regards, Dana.

Actually at the time I took those measurments I was just measuring voltage across a 1 ohm load resistor (no MOSFET connected) and I was expecting to see an increase in voltage as I added more pins, but that was not happening.

A quick schematic of that is attached (Current_Measurement)

I'm not sure what you mean by "does it meet the necessary level to get low Rdson at your switching freq?"

The Low Rdson is 4 Ohms max according to the data sheet.

The frequency that is oscillates at without a load is about 550 kHz (I informed you wrong earlier as I had forgotten I added another capacitor to my timing circuit) although this is faster than what it should be based on the timing circuit. For that I have a 100k resistor charging two 100 pF capacitors in parallel, then they discharge through a 10k resistor, so now it should take 20us to charge (thus sending a lowto my MOSFET for 20us) and then take 2us to discharge (sending a high to my MOSFET for 2us) therefore it should have a frequency of 45.5 kHz so there is something I am doing wrong there, I'll attach a Top Design in the next post.

Once I connect a load there really is no frequency because it is only sending a pulse when it needs to (as it should) except at startup when it is building up, during that time the frequency is about 550 kHz like it is without a load.

The amplitude of these pulses it about 4.24V, however the pulses become way less square when connected to the gate of the MOSFET (I'm assuming due to that gate capacitance?)

Here is the Top Design for the NOT gate configuration

For starters –

1) A 1 ohm R exhibits a dV of 1 mV / 1 mA.
2) The graph shows effective source Rdson of ~ 40 ohms.
3) The chip has a max Iddio of 100 mA (CY8C55).
4) The graph is incomplete, does not show Isrc at Voh = 0 for 5V operation.
5) The graph shows we get typical Ioh of 30 mA when Voh is < ~ 3.7 Voh.
6) So going from 1 output, 30 mA, to 4, 120 mA changes the 1 ohm from 30 mV to 120 mV. Is
that what you are seeing ?

I = C dV/dT, so use 120 mA, dV = 2.5V (Vgs to get decent Rdson), Cgd = 300 pF,
then dT = [( 300 x 10**- 12 ) x 2.5V ] / .12 A = 6.25 nS. The discharge case is even better because
outputs sink more current per pin.

You will see degradation in gate waveform because theoutput current drops dramatically as
Vgs approaches Vddio. So basically you have a RC exponential rise time in the waveform.

My reference to Rdson, gate level is required Vgson to get MOSFET turned on hard.
 

Regards, Dana.

One additional thought, consider using spice to simulate output and your

MOSFET circuit. You can get spice fror free that is crippled to small

simulations. And use a CD4000 or 74C inverter as Cypress substitute

for output pin.

Regards, Dana.

Thank you for you help, however what I ended up doing was using the PSoC to drive another MOSFET that it was more capable of driving (Vth of 1.2V instead of 4.5V) and now the system works) I would continue to pursue this issue more but I must move on to a different part. Again thank you for your replies they have been most informative.