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Verilog in PSoC3 - Sharing Variables
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Verilog in PSoC3 - Sharing Variables

kmmankad posted on 11 Jan 2012 5:29 AM PST
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274 Forum Posts

Hey,

So I'm trying to have code set some variables(an array,to be specific) in a verilog file,and the verilog code will then process that data,and clock out that processed data.How do I go about doing so?




Re: Verilog in PSoC3 - Sharing Variables

kmmankad posted on 11 Jan 2012 05:39 AM PST
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274 Forum Posts

I only have a few hours of Verilog experience,so I'll ask a few stupid questions on your replies.Just saying. :-P



Re: Verilog in PSoC3 - Sharing Variables

kmmankad posted on 11 Jan 2012 05:43 AM PST
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274 Forum Posts
by code setting variables I mean C code setting variables in some way which the verilog file can use them.

Re: Verilog in PSoC3 - Sharing Variables

abnoname posted on 12 Jan 2012 11:10 PM PST
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42 Forum Posts

 CPU (software) and hardware interaction (this is what you want) will work through status and control registers. For example you can instance a control register which will provide an api for cpu access and a digital out bus on the hardware side.






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