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One last change, update comments in main.c with below to fix
some errors I had in project description.
// This frequency counter is enabled by a simple gate, derived from timer compare output.
// Gate is set up as 1 sec high, 1 sec low, or 2 Hertz. The cycle starts as follows -
//
// 1) Counter period, CounterFreq24, is loaded with 0xFFFFFF, eg full count.
// 2) Gate timer compare out, TimerGateGen16, we will call it gate, goes high, enabling counter.
// 3) Counter counts down at Fx rate, until gate goes low.
// 4) Gate compare goes low, compare output set up to generate an interrupt - edge.
// 5) ISR sets a flag, GateLowFlag, returns.
// 6) In main() GateLowFlag flag is tested, if true, tells main() to service counter
// 7) Counter is stopped, read, reloaded with 0xFFFFFF. stopping counter allows the reload to
// immeadiatly update counter.
// 8) Value read is subtracted from 0xFFFFFF (16777215), that result is # counts in 1 sec gate = Hertz
// 9) Value converted to string, written to LCD
// 10) GateLowFlag flag is cleared, counter (CounterFreq24) start API is called. Note because gate is still
// low for 1 sec, it does not start counting right away until gate goes high.
//
// Notes -
//
// 1) ISR causes no latency as it occurs when gate goes low, disabling counter.
// 2) Gate is 1 sec, could be used as 100 mS to speed up, scale by 10 the reading.
// 3) Gate timer is 1 sec high, 1 sec low, for a 2 sec measurement latency. This
// can be shorted by changing the period, but keeping compare value same, so duty cycle
// of gate timer increases, eg. gate high time stays same, but low time shortend.
// 4) Accuracy is limited by internal 24 Mhz clk of PSOC. If you want high accuracy
// use a precision external clock.
// 5) Accuracy is also a f( frequency ), lower freqs = bigger error. Example if input is 10 Hz,
// Gate is 1 Hz, there is a minimum count error +/- 1 count, so effectively thats +/-
// 10% error at 10 Hz. Reciprocal counter technique can take care of that.
// 6) The ISR is a C ISR. boot.tpl must be modified in the root project directory to
// implement the jump vector for interrupt. The interrupt comes from last block in gate timer
// chain, TimerGateGen16, in this case DBB01, so that jump vector must be modified to "ljmp _yourISRname"
// 7) CounterFreq24 is 24 bit frequency counter, TimerGateGen16 is gate source to drive CounterFreq24 enable,
// TestFreq16 is a 16 bit timer used to generate a test frequency for debug/measurement, you can eliminate
// it and its associated code. CompnegISRsignal is a Digital Inverter to produce an ISR on TimerGateGen16
// compare output -edge.
// 8) If you need the digital block the DigInv uses to generate ISR on TimerGateGen16 compare output - edge
// then eliminate it. Set TimerGateGen16 interrupt property to interrupt on Tc, Insert into code that
// services ISR flag (GateLowFlag) a delay to fix fact Tc out ISR triggers before compare out (gate) falls
// to low (which disables CounterFreq24 from further counting). Delay would be >=1 clk of TimerGateGen16,
// which for 1 sec gate, is 1 / 5 Khz = 200 uS to make sure gate, hence CounterFreq24, finishes counting.
Regards, Dana.
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