Greatings Community!

I have faced with preaty strange fact.

I'm try`ing to create 10-chanel logic generator, based on counters whith two DMA chanels per each chanell.

first DMA refreshes Counter period (regulates perion lenght), second updates logic level (0/1).



the problem is :

some channels are reflected, some times are reflected and mirrored on another line.

(see pics below) 

imageshack.us/g/13/newfile0.png/

each pic made with only  one active Counter.

Can you tell me where am i wrong, or how to fix this problem?

I'm using CY8C3446AXI-099. 

Design is attached.

Best Regards,

Alex C.

Greatings Community!

I've spend a couple of days testing DMA channels. And I found what is the problem.

when I use 2 DMA channels, which are addressed to UDB blolcks(Counter x8) with 1 source eneble i'm getting two signals



DMA_7_Chan = DMA_7_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,
HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));
DMA_7_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_7_TD[0], 4, DMA_INVALID_TD, TD_INC_SRC_ADR);
CyDmaTdSetAddress(DMA_7_TD[0], LO16((uint32)src_ch7), LO16((uint32) Control_Reg_8_ctrl_reg__CONTROL_REG));
CyDmaChSetInitialTd(DMA_7_Chan, DMA_7_TD[0]);
CyDmaChEnable(DMA_7_Chan, 1);



DMA_8_Chan = DMA_8_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,
HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));
DMA_8_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_8_TD[0], 4, DMA_INVALID_TD, TD_INC_SRC_ADR);
CyDmaTdSetAddress(DMA_8_TD[0], LO16((uint32)src_ch8), LO16((uint32) Control_Reg_9_ctrl_reg__CONTROL_REG));
CyDmaChSetInitialTd(DMA_8_Chan, DMA_8_TD[0]);
CyDmaChEnable(DMA_8_Chan, 1);




DMA_16_Chan = DMA_16_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,
HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));
DMA_16_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_16_TD[0], 4, DMA_INVALID_TD, TD_INC_SRC_ADR);
CyDmaTdSetAddress(DMA_16_TD[0], LO16((uint32)src16), LO16((uint32) Counter_1_CounterUDB_sC8_counterdp_u0__D0_D1_REG));
CyDmaChSetInitialTd(DMA_16_Chan, DMA_16_TD[0]);
CyDmaChEnable(DMA_16_Chan, 1);


DMA_15_Chan = DMA_15_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,
HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));
DMA_15_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_15_TD[0], 4, DMA_INVALID_TD, TD_INC_SRC_ADR);
CyDmaTdSetAddress(DMA_15_TD[0], LO16((uint32)src15), LO16((uint32) Counter_2_CounterUDB_sC8_counterdp_u0__D0_D1_REG));
CyDmaChSetInitialTd(DMA_15_Chan, DMA_15_TD[0]);
CyDmaChEnable(DMA_15_Chan, 1);

Counter_1_Start();



Counter_1 - source of DMA16. But Oscilloscope shows 2 signals.



This happens only with UDB blocks.

Device: CY8C3446-AXI-099 prod.

Waveform and design are attached.