Thanks to Uday I've got some SPI transmission working, but I'm seeing a very strange problem with the transmission speed on SPI.

My device is a CY8C3866-ES3.  I'm using a SPIM Mode 0 @ 2.5 MBit, tx/rx buffer set to 96 bytes.  I fill TX with 80 bytes using SPIM_PutArray and then watch the transmission using my scope.

What I see is 8 bits getting clocked out in about 3.2 microseconds, then a 17 uSec gap before the next byte starts to transmit. 

I have two interrupts enabled besides the default: IRQ on Tx FIFO empty and IRQ on Rx FIFO full.

What could be stalling the SPI hardware to take this long before sending another byte?  This effectively is limiting my SPI transmission to under 1Mbit when I should be going 2-3 times faster.

Thanks,

Louis

When the SPIbuffer size is set to >4 bytes  , the internal interrupts are used to manage the software buffer. The delay that you are seeing is most probably the interrupt latency and delay in moving bytes from software buffer to hardware FIFO . Setting buffer size to 4 and moving data to and from FIFO using DMA(triggered by FIFO not full / Rx FIFO not empty ) might help to reduce the delay.

Regards,

Anu

 Thanks, Anu.  I'll give that a try.

Louis

 Anu: When will the Psoc3 SPI DMA example (http://www.cypress.com/?rID=38792) be available again?

Hi,

The DMA Example project that you wanted is available on the webpage.

-Udayan

My Case face similar issue,   PSoC3(CY8C3866-ES3)’s SPI Master component is used to interface with an external SPI Flash memory device. PSoC3 reduce the rx and tx buffers to 4 bytes and disable the SPI interrupts, it can obtain a minimum delay of around 6 us between bytes.  However, reading the status register and reloading the buffer in between 4-byte bursts takes about 20 us.  Is there any other way to more directly write to the SPI component to reduce the delay?

Can you give us some more information about your SPI configuration.

1. Clock speed of SPI Master,
2. Master Clock of PSoC and
3. Buffer size

-U2

HI,

Thinks for your reply. The delay is already fixed by using DMA to move date in/out from buffer. But there are other issue,  the data send to the I2S component from SPI memory by the DMA . There are used 4 DMA to transfer the data for 2 audio channel. The sound can be released but there have a noise randomly appeared. Threre may be a some problem on DMA or I2S. Would you have any material for me to know how the DMA working like the detial of TDs in DMA and how to read the coding of DMA and TD?

 I'd like some more detail about DMA TDs as well.  I'm looking at the SPI/DMA example code and application notes, and don't quite understand how to add code to perform some work when the DMA transfer is completed.

The SPI/DMA example uses a second chained TD to shut off the interrupt and finish the transfer, but in my project we have SPI Slave Select muxxed to various peripheral devices.  I need to be able to toggle the SS lines under software control, or have an interrupt handler do it.

Most of Cypress' PSoC SPI examples are done by having a SPIM and SPIS on the same chip, which is nice for learning, but doesn't give a lot of real-world example when interfacing the PSoC to other external devices over a hardware bus.

The AN52705 - Using DMA on PSoC® 3 and PSoC 5 ,this application note describes the basic and important steps in configuring the DMA. The application note is associated with four projects that describe how to configure DMA to transfer data in four different scenarios. The important DMA APIs and DMA configurations are illustrated through the following example projects.