68013A(slave_ Asynchronous)+blackfin(bf518_DSP_master)

I configure the 68013A into slave mode.EP2 is out endpoint. EP2 is configured into 2*512, 8bits, auto. And I configure tha  the EP2 have no data which the FLAGC is low level and there is some data FLAGC will become high level.Now I have two questions.

1.If send the data(0x17, 0x89,0xcf)  to the EP2 in order.  I know that

EP2FIFOBUF[0]=0x17, EP2FIFOBUF[0]=0x89, EP2FIFOBUF[0]=0xcf. If DSP is sucessed in reading EP2 fifo three times ,then  EP2FIFOBUF[0/1/2]=0x00 or  EP2FIFOBUFER have no changed EP2FIFOBUF[0]=0x17, EP2FIFOBUF[0]=0x89, EP2FIFOBUF[0]=0xcf???  And is there any register about that privious EP2FIFOBUF is cleared if read it?

2.I have question about when the FLAGC pin become low level?

I have sent three data(0x17, 0x89,0xcf), when the DSP read EP2 fifo 3 times the FLAGC become low??? Or DSP read EP2 fifo 512 times the FLAGC become low(EP2 is configured into 2*512) ???

 Yes, I have put endpoints into valid configuration.

 SYNCDELAY;                    // see TRM section 15.14

  EP2CFG = 0xA2;   //1010_0010 // BUF[1:0]=10 for 2x buffering

  // EP6 512 BULK IN 2x

  SYNCDELAY;                    // 

  EP6CFG = 0xE2;   //1110_0010 // BUF[1:0]=10 for 2x buffering

  // EP4 and EP8 are not used in this implementation...

  SYNCDELAY;                    // 

  EP4CFG = 0x20;  //0010_0000   // clear valid bit

  SYNCDELAY;                    // 

  EP8CFG = 0x60; //0110_0000   // clear valid bit

The picture of attachment is that when I download the code into the 68013a

 Anyone can help me?

 Hi,

Please paste Td_poll and Td_init part of your code.

-PRJI