Hi 

My fx2lp is Slavefifo with fpga and sensor. 

Fx2lp out  garbage data (all 0)  when sensor's hsync is low. 

How am i supposed to handle these problem?

Can i use hsync instead for slwr? 

 Connect Frame Valid to Slave select and Line valid to Slave write

 Check out this app note to understand the UVC protocol

http://www.cypress.com/?docID=42773

 Ok   What happen slavefifo's flagd low and slwr low?

And how should i handle of this case?

 In that case, the data received on the data lines is stored and sent to host when a sunc signal is received on PKTEND

 Hi i don't understand exactly.

Could you please for more detail with example ?

 the data received in slave fifo mode is stored in the IN Endpoint buffer.

A SYNC signal on the PKTEND pin commits this buffer to the host. 

If the buffer is full and not commited to host yet, the FLAGs state will indicate that the the Endpoint buffer is full and the Master device on slave fifo interface should stop sending data. Otherwise the  packets will be dropped.