Hi everyone!

I am trying to design a FPGA high speed data acquisition system based on USB communication to solve the problems of
high speed data acquisition and transmission.The USB2.0 I use is CY7C68013A. And I want to use the slave fifo mode(Synchronous or Asynchronous) in my design.

However, I am a green hand; I do not know how to design a Firmware for the USB. What's more, the computer interface is totally unfamiliar for me. I know the slave fifo is a little case for you experts. But the EDA is really difficult for me being a researcher in optics. Somebody can give me the fifo project (if you ever did) to help my learning and design? Of course, any suggestions about my design are appreciated.

If you want to give me some useful materials, you can send it to me Email: beiming200906@gmail.com.

Thank you guys.

My FPGA is EP3C10E144C8 from Altera-Cyclone III.

Hi,

Please refer to the following application note:

http://www.cypress.com/?rID=43046

FPGA code and FX2LP firmware are attached to that application note.

Here, you just need to port the FPGA code to your Altera one.

Thanks,

Sai krishna.

Thank you for your imformation. I will have a try.

Hi RSKV,

First of all, thank you for your help in the forum.  I am learning the AN61345 following your suggestion. Because my FPGA is EP3C10E144C8 from Altera-Cyclone III, I encountered some problems when I refer to you design in AN61345. I hope to get your further help with my confusions. I am so sorry to trouble you and my problems are as follows:

No.1: about the clock issue. 

As I know, in the design with Altera FPGA we can generate the clock from PLL. So, I think I can get the global clock of FPGA from PLL; then the FPGA can supply the IFCLK for the FX2LP. Is that right? And then, my confusion comes. How do I modify the codes in the file fx2lp_slaveFIFO2b_loopback_fpga_top.v? I do not understand the function of clk_wiz_v3_6.v clearly and the modification is difficult.

No.2: the function of ‘done’? I have referred to the handbooks of FPGA and USB and I did not find a pin named ‘done’; so I do not know how to make the pin mapping. By the way, the ‘done’ is equal to ‘PKTEND’, right?

What’s more, I want use the Verilog HDL codes, should I just copy and modify fx2lp_slaveFIFO2b_loopback_fpga_top.v using another tool-Quartus II and ignore other files in folder ‘Loopback’? I have no idea.

Looking forward to hearing from you！