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Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

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Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	alermto posted on 22 Apr 2013 6:24 AM PST Senior Member 14 Forum Posts

Hi,

I have just read the AN61345 by Rama Sai Krishna V, which explains and provides examples for a complete configuration of a Host + FX2LP + FPGA system. I saw in the Document History that there used to be a version with details about the Virtex5.

I am currently trying to develop a system like the one described in that application note on a Avnet Virtex5 board, and was wondering if that version of the document is still available.

Thank you so much.

Regards,

Alessandro Angelino

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	NIKL posted on 24 Apr 2013 10:06 PM PST Cypress Employee 148 Forum Posts

Can you please explain your application?

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	NIKL posted on 24 Apr 2013 10:10 PM PST Cypress Employee 148 Forum Posts

The older projects had a timing voilation and using internal IFCLK in FX2LP. So the projects had been updated.

The new projects use external IFCLK on FXLP.

If you still want the files, you can mail nikl@cypress.com or rskv@cypress.com

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	NIKL posted on 24 Apr 2013 10:11 PM PST Cypress Employee 148 Forum Posts

Check this post for info on the latest projects:

http://www.cypress.com/?app=forum&id=167&rID=78668

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	alermto posted on 24 Apr 2013 05:34 AM PST Senior Member 14 Forum Posts

Hi, thank you for your help.

The project I'm working on is based on a pre-existing design which worked with the serial port. Now I would like to upgrade it to a USB connection, using the CyAPI library on the host side.

I just need quite a little amount of data to be sent from the FPGA to the PC and other data on the way back - all data is provided by the FPGA itself, so no particular computation is needed by the USB controller. I saw the AN61345 and realized that the slave mode is probably the most suitable for my design, but this is the very first time I'm approaching USB, so I was looking for something very close to my configuration in order to have more material to start from.

I will also read the link you posted, and maybe try to send an email for those older versions of the application note.

Do you have any suggestion for the implementation of such a system on a Virtex5 Avnet board? Thank you!

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	alermto posted on 24 Apr 2013 06:37 AM PST Senior Member 14 Forum Posts

In particular, my problem is related to the pin assignment in the .ucf file, which I don't know how to adapt to my board.

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	NIKL posted on 24 Apr 2013 10:14 AM PST Cypress Employee 148 Forum Posts

Pin assignment depends on your hardware.

Either you already have a hardware and then you decide which pins you want to use and put it down in your ucf.

Or first decide your pin assignment, create an ucf and then design your hardware accordingly.

Let us know details on your interface so that one of us can assist you in deciding the pin assignment.

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	alermto posted on 29 Apr 2013 05:16 AM PST Senior Member 14 Forum Posts

Yes, I'd really appreciate someone's help about this topic.

The hardware I'm working on is an Avnet board, the V5LX50, with a Xilinx XC5VLX50-FF676 FPGA and a Cypress CY7C68013A-100AC USB Microcontroller. I would like to modify the ucf file given with the design example related to the AN61345 in order to make it compatible with the board I'm using... but actually I don't know where to start from!

Thank you very much in advance!

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	NIKL posted on 30 Apr 2013 11:52 PM PST Cypress Employee 148 Forum Posts

alemrto

In the loopback example (path: \AN61345 - Source files for FPGA code and FX2LP Firmware\001-61345\FPGA Source Code_Verilog\Loopback\fx2lp_loopback_proj\) you can find a ucf file with the following content:

NET "clk" LOC = "K14" |IOSTANDARD = LVCMOS33 ;

NET "clk_out" LOC = "J14" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<0>" LOC = "C16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<1>" LOC = "C15" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<2>" LOC = "D16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<3>" LOC = "D14" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<4>" LOC = "E13" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<5>" LOC = "E12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<6>" LOC = "F16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<7>" LOC = "F15" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<8>" LOC = "P10" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<9>" LOC = "N12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<10>" LOC = "P12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<11>" LOC = "N5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<12>" LOC = "P5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<13>" LOC = "L8" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<14>" LOC = "L7" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "fdata<15>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "faddr<0>" LOC = "T5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA4

NET "faddr<1>" LOC = "N11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA5

NET "slrd" LOC = "K11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "slwr" LOC = "J11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "sloe" LOC = "T3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA2

NET "flaga" LOC = "F12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "flagd" LOC = "T10" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

NET "done" LOC = "G11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	NIKL posted on 30 Apr 2013 11:56 PM PST Cypress Employee 148 Forum Posts

To explain the signals:

"clk" is the IFCLK (input clock for Slave fifo interface; can be internal/external); on ZTEX board this is connected to "K14" pin of FPGA.

In you case you will to find which pin of FPGA is IFCLK of Fx2lp connected to and replace K14 with the pin.

Make the similar changes in the verilog code

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	NIKL posted on 30 Apr 2013 12:05 AM PST Cypress Employee 148 Forum Posts

Similarly for

clk_out: clock out from FX2LP; this is input clock to FPGA PLL; a phase shift clock is generated using clk_out of FX2LP and given to IFCLK of Fx2LP

fdata: slave fifo data; can be 8/16 bit data;

faddr<0>, <1>: is slave address

slrd, slwr and sloe are general slave read, write and enable signals

Flag a/d: flags to indicate fifo status

done: is high when FPGA configuration is done; in Fx2lp firmware this bit is polled for (check code in TD_Poll function); when this bit is high the IFCLK is changed from internal to external in FX2LP firmware (because if IFCLK is supposed to be External, the IFCLK should already be present when IFCLK is configured as external)

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	NIKL posted on 30 Apr 2013 12:07 AM PST Cypress Employee 148 Forum Posts

for all of the above signals of FX2LP you need to find the corresponding connections on FPGA on your board and make the corresponding changes in ucf and verilog code.

Please let me know if the information helped.

Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

	PRJI posted on 30 Apr 2013 12:13 AM PST Cypress Employee 333 Forum Posts

Hi,

UCF file is shown below

NET "clk" TNM_NET = "clk";