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68013A slavefifo
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68013A slavefifo

nbb posted on 03 Apr 2013 12:09 AM PST
Member
2 Forum Posts

recently,I have worked on 68013A communicating  with DSP(28335 from TI) in slavefifo mode.The wordwide is 16 bits,but the DSP just can receive high 8 bits,it lost low 8 bits.I can not find where is the problem.NEED HELP!!!SOS!!

the fllow is my TD_Init().

void TD_Init(void)             // Called once at startup
{
  CPUCS = 0x12 ; // set the CPU clock to 48MHz
  SYNCDELAY;
  IFCONFIG |= 0xCB; //内部时钟,48MHZ,异步传输
SYNCDELAY;
 REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
  SYNCDELAY;
//端点配置           
  EP2CFG = 0xA2;  //OUT端点,2缓冲
  SYNCDELAY;                   
  EP4CFG = 0x7F; //该端点无效
  SYNCDELAY;                   
  EP6CFG = 0xE2; //IN端点,2缓冲
  SYNCDELAY;                   
  EP8CFG = 0x7F; //该端点无效
 
  //端点复位
  SYNCDELAY;                   //
  FIFORESET = 0x80;// activate NAK-ALL to avoid race conditions
  SYNCDELAY;                    //
  FIFORESET = 0x02;             // reset, FIFO 2
  SYNCDELAY;
  FIFORESET = 0x04;
  SYNCDELAY; 
  FIFORESET = 0x06;             // reset, FIFO 2
  SYNCDELAY;                  //                   //
  FIFORESET = 0x08;
  SYNCDELAY;
  FIFORESET = 0x00;             // deactivate NAK-ALL
  SYNCDELAY;

 OUTPKTEND=0x82; //强制OUT包结束
 SYNCDELAY;
 OUTPKTEND=0x82; //强制OUT包结束
  SYNCDELAY;
//EP2BCL=0x80;
 //SYNCDELAY;        
//EP2BCL=0x80;
// SYNCDELAY; 
  //端点FIFO配置
  SYNCDELAY;
  EP2FIFOCFG = 0x11;    // 自动输出,16位数据
  SYNCDELAY;                              
  EP6FIFOCFG = 0x0D;   // 自动输入,16位数据
  SYNCDELAY;
  INPKTEND=0x06;
  SYNCDELAY;
 
 //设置FLAGB为端点2的空标志
  PINFLAGSAB = 0x80;  // FLAGA - PF, FLAGB - fixed EP2EF 
  SYNCDELAY;
  //引脚配置为片选
  PORTACFG=0x40;
  SYNCDELAY;
 EP6AUTOINLENH=0x02;
  SYNCDELAY;
  EP6AUTOINLENL=0X00; //set the packet size 512字节
  SYNCDELAY;
}
 

 

as the figure shows ,it lost low 8 bits data .




Re: 68013A slavefifo

RSKV posted on 03 Apr 2013 01:56 AM PST
Cypress Employee
848 Forum Posts

Hi,

Endpoint configuration looks fine to me.

You just need to change following registers to support 16-bit.

For 8-bit:

EP2FIFOCFG = 0x10;           
SYNCDELAY;                    
EP6FIFOCFG = 0x0C;           
SYNCDELAY;

To support 16-bit:

EP2FIFOCFG = 0x11;          
SYNCDELAY;                  
EP6FIFOCFG = 0x0D;          
SYNCDELAY;

Are you able to see the right data using 8-bit data bus?. If yes, then you just need to do the changes that I mentioned above.

Can you please re-check the way you are reading on processor side whether you are reading whole 16-bits.

Thanks,

Sai Krishna.

 

 

 



Re: 68013A slavefifo

nbb posted on 06 Apr 2013 06:13 AM PST
Member
2 Forum Posts

Dear Sai Krishna

Thank you for your reply.In 28335 processor,I have defined an areay (unsigned int data[512]) to receive data from 68013A's out endpoint. the processor get data from the address directly,as data[i]=*USB_FIFO2.when i send data (12 34 56 78) to processor using Cypress USB Console,i can find data[1]=0x3400,data[2]=0x7800 in DSP processor.it lost 12 and 56.when i use 8 bits wordwide,the problem is the same .I think the problem should be  in DSP processor,although i do not kown where.

thank you again;

binbin nie from china ;






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