Hi,

I'm working on a project, where we connected an Aptina optical sensor to the FX2 in GPIF-mode with external clock-source.

We connected

the LINE_VALID to RDY0,

the FRAME_VALID to RDY1

the pixel-clock to the IFCLK

and the pixel-data bus to D0-D7

pins of the FX2.

It works really well on the CY3681 developmen-kit with an rather old revision of the FX2 with 128-pins.

However on other board, with rather new FX2LP with 56-pins, the GPIF-wave once started will never get done, when I source the GPIF from the external clock-source (sensor generated pixel-clock).

When I experimentally switch the GPIF clock-source to internal clock, the wave will get done. In this case, the data are nonsense (because the GPIF is not synchronized to the pixel-clock) but I can see that my decision states (waiting for the start of the frame and start of the line) works...

On both boards I have connected the logic analyzer to the respective pins of the FX2 and can see that the signals from the sensor are the same. On the development-board, I see the states of the wave changing too. This I can't verify on the other board with the 56-pin version of FX2.

Can anybody please give me any hint, where else I should look?

Are there any specific differences between the different versions of the FX2, that might cause such a problem?

Any help is greatly appreciated.

Hi,

If you are using interface clock from external source (image sensor in your case) then it should be available before you configure IFCONFIG.7. The external IFCLK source must be present before the firmware sets IFCONFIG.7 = 0

Please check whether you are meeting this condition or not.

Thanks,

Sai Krishna.

Hi,

thanks for the quick reply.

In the meantime, I've been searching myself for the differences of the two versions of the FX2 (128-pin vs. 56-pin) and the two boards.

There is one significant difference between the setups: the 128-pin development-board (working) is bus-powered and the 56-pin (not working) board is self-powered. That would maybe explain that the GpifInit() would get called before the pixel-clock gets stable... I will check that.

There is one other thing, that caught my attention, while I was checking the configuration of the wave in the GPIF-Designer.

My wave uses the TCxpire/RDY5 signal. Before I start the wave, I'm setting the desired transation count and within the wave I'm checking the TCxpire signal to switch to the idle-state again. However, when I change the part-setting in the GPIF-Designer to the FX2 with 56-pin, this signal is not available anymore in the block-diagram.

I didn't find any specific information in the TRM, can you please tell me, if the TCxpire signal is available on an FX2LP with 56-pins?

Thanks for any help in advance.

 Hi,

RDY5/ TCExpire signal is not available in 56 pin package of FX2LP.

Regards,

Gayathri

Hi,

so basically, any wave depending on the transmission count (internal TCxpire) mechanism will noch work with that variant of FX2.

Am I right?

Regards,

Pavol.

Hi,

so basically, any wave depending on the transmission count (internal TCxpire) mechanism will noch work with that variant of FX2.

Am I right?

Regards,

Pavol.

 Hi,

SOrry for the confusion caused. What I meant was RDY5 signal (an external RDY signal) is not available in 56 pin package. However, TCXpire being an internal RDY signal, is available even in 56 pin package. If you choose 56 pin FX2 package in GPIF designer, you have the following options to use as RDY signals in a decision state: RDY0, RDY1, TCXpire, FIFOflag, IntRdy.

Regards,

Gayathri

 PFA screenshots from GPIF designer.

Hi,

thanks for the reply. I was just wondering because my wave (using TCxpire) seem to work with the internal clock-source even with the 56-pin FX2.

Yesterday, I was experimenting with the GPIF init. I moved the call to GpifInit() from TD_init() to TD_poll() and postponed it to get called only after SetConfiguration-Request from the host. At that point the pixel-clock (external GPIF clock-source) should definitely be stable. However, I still couldn't see that the wave finishes. I even simplified the wave to have only two decision points, which recognizes the start of the first line of the image and then GPIF should go Idle (done). As I wrote earlier, I see the signals from the sensor on the logic analyzer and they are well. However the sensor clock is too fast to see it properly on that analyzer. On the other side, cross-checking on the other board shows that the wave works...

Has anyone any further ideas, that could cause the problem?

Any help or suggestions are appreciated very much.

Pavol.

 Hi,

What is the value of Pixel clock which you are using? Is it in the range 5 - 48MHz? 

Regards,

Gayathri

Hi guys,

just wanted to report that everything works well now. The problem was the setting of the "Sync RDY to IFCLK" option in the "GPIF Designer". I was experimenting with that on the developent board (with the 128-pin version) and disabled the option to see if GPIF reacts faster to the RDY-input signals and left it disabled as I moved to the other board (with 56-pin version of the FX2).

Everything works well and stable on the board with the 56-pin version of FX2 with the external clock source, when I enable this option. When I leave it disabled the GPIF doesn't seen to complete the wave there, even if it doesn't seem to have any impact on the development board.

There seem to be a difference in how the GPIF works with external clock source between the two FX2 versions, depending on  the option .

Thank you for the ideas and time.

Regards,

Pavol.

 Thanks for posting.