I am trying to get an FPGA interface working on a FX2LP. I have used the application note AN61345 Spartan 6 design, just changing the FPGA pins to match my own. If I use the USB control centre to send some bytes to the FX2LP it reports that it worked fine. However when I try to read them back it gives the following error.

BULK IN transfer failed with Error Code:997

Can someone tell me what this means? I am a bit surprised that the example design would not just work out of the box.

Thanks

Jon

 Hi,

Are you using ZTEX module? Does streamer example work ? How many OUT transfers could you perform? 

Could you please probe the interface lines and let me know your observations? 

-PRJI

 I managed to get it going. There was some setting that were not correct.

I have the same problem.

Which settings?

I'm using a Zetex module.

 I'm not using a Ztex module. If you post your descriptors I may be able to help.

Jon

Hi, 

Does streamer example work ? How many OUT transfers could you perform? 

Could you please probe the interface lines and let me know your observations? 

-PRJI

 Hi Richie72

Is it a Spartan6 Ztex module you are using?

Thanks

Nikhil

Yes, I'm using the Spartan6 Zetex 1.11 module.

I'm trying to run the examples of the AN61345 application notes, without any changes.

@prji: I can execute Bulk Out Transfer 4 times.

The streamer example don't work.

 Hi,

 Since EP2 OUT is 512 x 4 you will be able to do 2K of OUT transfer, these packets go to OUT buffer of FX2LP not to FPGA. It seems your FPGA is not configured properly or not getting proper voltage on control or data pins. Check Flag(FlagD and FlagA) status after each Out transfer, it should change after 4th transfer in case of dataloopback example. As the data transfer in the Streamer example is unidirectional I would suggest you to start debugging with this example, it would be easier to isolate issue. Probe on data lines to ensure FPGA has been configured properly and is pumping data to FX2LP.

-PRJI

 Richie

How are you loading the FPGA bit stream?

Are you first loading the FX2LP image and then loading the FPGA bit-stream (through JTAG) as mentioned in the App. Note?

Thanks

Nikhil

 Richie

Please check out the "variants" mentioned in the following site:

http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html

Which variant are you using?

Thanks

Nikhil

I'm using the Ztex Module 1.11c with the LX25  with a Experimental Board 1.2. 

I’m trying to run the examples (Loop Back, Streamin) like you described it in the AN61345 paper.

Everything works fine, but the BULK IN transfer fails with the following error:

                BULK IN transfer

BULK IN transfer failed with Error Code:997

 What does that error means?

I have registered the ZETEX VID and PID in the CyUSB.inf.

Then downloaded the slave.hex to the RAM via USB.

After that I have downloaded the bit-streams with the XILINX Platform Cable USB II and the impact tool.

BULK OUT works fine, but the BULK IN transfer always fails.

In the CyConsole the FX2 appears as SLAVE FX2, is that ok?

Endpoints 2 and 6 are configured:

                                               <ENDPOINT>

                                                               Type="BULK"

                                                               Direction="OUT"

                                                               Address="02h"

                                                               Attributes="02h"

                                                               MaxPktSize="512"

                                                               DescriptorType="5"

                                                               DescriptorLength="7"

                                                               Interval="0"

                                               </ENDPOINT>

                                               <ENDPOINT>

                                                               Type="BULK"

                                                               Direction="IN"

                                                               Address="86h"

                                                               Attributes="02h"

                                                               MaxPktSize="512"

                                                               DescriptorType="5"

                                                               DescriptorLength="7"

                                                               Interval="0"

                                               </ENDPOINT>

In the USB Data Streamer application there is no choice for the endpoint configuration.

 Hi,

 As PRJI suggested, please probe the lines.

You could also probe PA1 of FX2LP to check if this pin is high.

Probably the FPGA is not configured properly or might be that FPGA has gone bad.

If you have another ZTEX 1.11 module, you could try running the same examples on the other board.

Thanks

Nikhil

 Hi

I tested the bit-streams on web. There seems to be a bug in the pin-mapping.

Please create a tech-support case, if you require the projects ASAP.

In any case we will be fixing the projects latest by today or tomorrow ( the process has been initiated).

I will drop a message as soon as the correct projects are available on web.

Thanks for brinnging it to our notice.

Thanks

Nikhil

Nice to hear that I'm not too stupid to run an example!

THX!

 Richie

can you please give me your email id?

Thanks

Nikhil

With the new .bit files everything works fine!

THX

 Great! The documentation and the files will be uploaded on web soon!