Hi

I have used a GPIF Master Mode example from another forum and altered it for my purposes. The big picture of what i want to do is have data being transferred from the USB port(master) to the GPIF and that data then sent out on the data bus to an FPGA. At the moment what i am having trouble with is i want to send some bytes (using the control center) to an OUT endpoint and that data then sent to the GPIF, then outputed 8 bit data bus (D0:D7 --> GPIO[0]-GPIO[7]). I also want to be able to recieve some bytes (using the control center) from an IN endpoint. I want the GPIF to not interfere with any data and just let the data pass to the data bus.

The main problems i am having are:

1) How should the 2 endpoints/sockets be setup

2) What DMA channel (i.e AUTO,MANUAL, etc..) should be used. 

3) Do we use IN_DATA action or DR_DATA action in one of the states in the state machine. 

4) Do i use socket or register in the 2 actions above.

Ive been trying for weeks now and i cant seem to get it working, so can someone please help me that would be much apreciated.

Thankyou :)

Hi,

As per my understanding, your data path is:

FPGA <-> FX3 <-> PC

Is there any special reason for going with GPIF II master mode implementation?

You could do this easily with the help of following application note:

http://www.cypress.com/?rID=51581

Please go through this and let me know if you are looking at a different implementation.

Thanks,

Sai Krishna.

Thanks for the reply,

Thats sorta what im looking for, its just more complicated state machine and the FX3 must be a master. At the moment all i want to get working is to write some bytes from the control center (which is successfully writing to the OUT endpoint) and route that data to the GPIF data bus and view the data bits (DB[0]-DB[7]) on the oscilliscope. The data is being transfered to the OUT endpoint but i cannot see anything on the data bus. I just firstly need setup the state machine to acheive this, like:

1) What are the main actions required(i.e. DR_DATA or IN_DATA or both?)

2) Do i need to check the DMA flags or DMA_Thread_Ready

3) Are there any neccessary API calls, etc...

Thankyou for your help :)

Hi,

Take the data path from PC to FPGA

PC -> FX3 OUT endpoint -> FPGA

You need to create a DMA channel between USB producer socket and PPORT consumer socket. You can go for AUTO or MANUAL channel. But if you go for MANUAL then you should have a DMAcallback function and there you should be committing the buffer.

Coming to the action that you need to perform in the GPIF II state machine, You need to add DR_DATA action to a state where you want to drive data to FPGA.

Now take the other way. i.e from FPGA to PC

FPGA ->FX3 IN endpoint -> PC

You need to create a DMA channel between PPORT producer socket and USB consumer socket. As said earlier, You can go for AUTO or MANUAL channel.

Coming to the action that you need to perform in the GPIF II state machine, You need to add IN_DATA action to a state where you want to sample data into FX3.

You need to make use of DMA flags (DMA_thread_Rdy) in both of these data paths to know whether the buffer has data to transmit (FX3 ->FPGA) or the buffer is free enough to accept more data (FPGA -> FX3).

Regards,

Sai kirshna.

Ok its all working fine now, problem was i wasnt checking the DMA_RDY_THR flags. I just have one problem in my IDLE state i have to outgoing transitions one to start read and other to start writing. one transition equation is "DMA_RDY_TH0" and the other i have "DMA_RDY_TH3". But the GPIF desginer shows an error message "DMA_RDY_TH0 and DMA_RDY_TH1 cannot used together in the outgoing equations from the state IDLE ". Does this mean i have to develop 2 different states machines one or read and one for write ?? and if so how will i go about loading and starting each state machine based read or write operations.

Thankyou for your help :)

Hi,

Good to hear that.

Coming to your new problem, I think you can avoid that by having two idle states. In first idle state you check for "DMA_RDY_TH0" and go to read or write based on your logic. if not DMA_RDY_TH0 then go to second idle state there you check for "DMA_RDY_TH3" and go to read or write based on your logic. If not DMA_RDY_TH3 then go back to first idle state.

Let me know if this does not work for you.

Thanks,

sai krishna.

i have attached my state machine. it now says in timing window "invalid state machine path for the simulation for the state IDLE_WRITE:

RESET --> IDLE_READ --> IDLE_WRITE --> WRITE

Thankyou :)

 Its all good now i fixed the problem by just using an input to the fx3 and that was used in the transition equation to start the writing or reading operations. Thankyou verymuch for your help and if i have any more problems ill let you know.

Good to hear that everything is working at your end.

Regards,

Sai Krishna.