Hello,

I have connected a FPGA to the FX3 in 32-Bit mode at 100MHz (SlafeFifoSync). I did read the documentation and a lot of forum articles already but still have some questions. 

I have to transfer large data blocks (several Megabytes) from the FPGA to the FX3. I will implement a DMA-Auto-channel from P-Socket to U-Socket.

To reach max. speed I will use a large burst size, let’s say 256 DWORDs. 

Can I do the following?

1.) Configure FLAGA to FIFO full and FLAGB to a Watermark of 256-DWORDs.

2.)  When FLAGB is OK I will  burst 256 DWORDs to the FX3.
       When only FLAGA is OK I will transfer 1 DWORD to the FX3.

3.) After the transfer I am adding a 3 Clocks delay for the FLAGs to become valid.

4.) I continue with Step 2

If this is possible, what will be a good configuration for the DMA-Buffers? 
What is the right “burst” parameter in CyU3PGpifSocketConfigure?

What about the PKTEND?

When I am transferring a multiple of 1024 Byte (SuperSpeed) I don’t have to set PKTEND? When it is not a multiple of 1024 Byte I have to set PKTEND with the last transfer or a ZLP after that? Is it a problem to send a ZLP after each transfer regardless of the length?

I am still waiting for my board, but I am working on the FPGA and it would be nice to get some information about this. It will help me to design the FPGA-FX3-Interface. 

For maximum data transfer rate you have to request as large blocks as possible at the host side. The packets per burst ist max. 16 and this is the fastest. When you set it to 16, the DMA buffer also have to set to 16 times the packet size, 16k Byte in SS mode. So you can set the watermark level to 4 and as this is a offset, it will always signal the fpga if there are less then 4 words to full. In this case you can slow down the writing to one write every 4 clock cycles and monitor the full flag. This is also described in the slave fifo app note (I think, Cypress took this from a former posting of me). I implemented the full/partial full is this way and it works perfect in DMA auto mode. I can transfer terabytes without error. But I think you should not use the max. PCLK of 100MHz, as the setup time for SLWR is 2ns but the FLAG propagation delay is in the worst case 8 ns. So the FPGA has 0 ns for the logic path :(

Thank you for the reply Chris. I see what you mean and it sound plausible to me.

I have tried to handle the data transfer like I am doing it inside the FPGA. There I am using 2 flags. One says I can do a burst the other says I can do a single transfer. So I do not need to watch any flags during the transfer. Disadvantage is a short pause after each transfer, but if the burst is large enough, this is not really a problem.

When I am using your suggestion, I have one question. You say I should lower the frequency, because of the FLAG delay.  Isn’t it possible to set the watermark to 5 or 6  instead of 4 to give the FLAG-Signal some more time? 

Of course you can set the watermark level higher. You´re right, I think the problem with the setup time is solved if you do only single transfers and watch the full flag after a single word transfer. Different from the FX2 it is not really possible to fill the buffer completely with only one flag. At the moment I cannot test the 100MHz PCLK as we are using the FX3 DVK with a samtec cable connected to a Xilinx board and its FMC connector. With more then 70MHz I get data errors over the 4 inch cable.