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Question about Synchronous Slave FIFO Read Sequence.
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Question about Synchronous Slave FIFO Read Sequence.

kommy2 posted on 16 Oct 2012 10:48 PM PST
Member
2 Forum Posts
Hello,
In our system, FX3 and FPGA are connected by Synchronous Slave FIFO interface(32bit bus).
We have a question about the sequence for performing reads from it.
If a master(FPGA) starts asserting of SLCS and SLRD simultaneously, is it a problem for a slave(FX3)?
In Figure3 of the Application Note(AN65974_001-65974.pdf), it begins to assert SLRD after 1 cycle of PCLK from SLCS.
And, the description about the timing is not found besides the figure.
Do we have to design according to the timing of this figure?
Regards,
kommy2



Re: Question about Synchronous Slave FIFO Read Sequence.

RSKV posted on 16 Oct 2012 12:08 AM PST
Cypress Employee
655 Forum Posts

Hi Kommy,

FX3's slaveFIFO interface should work normally even if you assert SLCS, SLRD, SLOE simultaneously.

Thanks,

sai krishna.

Re: Question about Synchronous Slave FIFO Read Sequence.

kommy2 posted on 24 Oct 2012 10:45 PM PST
Member
2 Forum Posts
Hi sai krishna,
Thank you for your reply.
We understand your answer about our question.
Regards,
kommy2



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